};
u32 ems;
u32 ems_mode;
+ struct amd76x_error_info discard;
debugf0("%s()\n", __func__);
csrow->edac_mode = ems_modes[ems_mode];
}
- /* clear counters */
- pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS, (u32) (0x3 << 8),
- (u32) (0x3 << 8));
+ amd76x_get_error_info(mci, &discard); /* clear counters */
if (edac_mc_add_mc(mci)) {
debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
int rc = -ENODEV;
int index;
u16 pci_data;
- u32 stat32;
- u16 stat16;
u8 stat8;
struct mem_ctl_info *mci = NULL;
struct e752x_pvt *pvt = NULL;
u32 dra;
unsigned long last_cumul_size;
struct pci_dev *dev = NULL;
+ struct e752x_error_info discard;
debugf0("%s(): mci\n", __func__);
debugf0("Starting Probe1\n");
pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
/* clear other MCH errors */
- pci_read_config_dword(dev, E752X_FERR_GLOBAL, &stat32);
- pci_write_config_dword(dev, E752X_FERR_GLOBAL, stat32);
- pci_read_config_dword(dev, E752X_NERR_GLOBAL, &stat32);
- pci_write_config_dword(dev, E752X_NERR_GLOBAL, stat32);
- pci_read_config_byte(dev, E752X_HI_FERR, &stat8);
- pci_write_config_byte(dev, E752X_HI_FERR, stat8);
- pci_read_config_byte(dev, E752X_HI_NERR, &stat8);
- pci_write_config_byte(dev, E752X_HI_NERR, stat8);
- pci_read_config_dword(dev, E752X_SYSBUS_FERR, &stat32);
- pci_write_config_dword(dev, E752X_SYSBUS_FERR, stat32);
- pci_read_config_byte(dev, E752X_BUF_FERR, &stat8);
- pci_write_config_byte(dev, E752X_BUF_FERR, stat8);
- pci_read_config_byte(dev, E752X_BUF_NERR, &stat8);
- pci_write_config_byte(dev, E752X_BUF_NERR, stat8);
- pci_read_config_word(dev, E752X_DRAM_FERR, &stat16);
- pci_write_config_word(dev, E752X_DRAM_FERR, stat16);
- pci_read_config_word(dev, E752X_DRAM_NERR, &stat16);
- pci_write_config_word(dev, E752X_DRAM_NERR, stat16);
+ e752x_get_error_info(mci, &discard);
/* get this far and it's successful */
debugf3("%s(): success\n", __func__);
int drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
u32 dra;
unsigned long last_cumul_size;
-
+ struct e7xxx_error_info discard;
debugf0("%s(): mci\n", __func__);
pvt->tolm, pvt->remapbase, pvt->remaplimit);
/* clear any pending errors, or initial state bits */
- pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
- pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
+ e7xxx_get_error_info(mci, &discard);
if (edac_mc_add_mc(mci) != 0) {
debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
*/
clear_pci_parity_errors();
- /* perform check for first time to harvest boot leftovers */
- do_edac_check();
-
/* Create the MC sysfs entires */
if (edac_sysfs_memctrl_setup()) {
edac_printk(KERN_ERR, EDAC_MC,
int index;
struct mem_ctl_info *mci = NULL;
unsigned long last_cumul_size;
+ struct i82860_error_info discard;
u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
}
- /* clear counters */
- pci_write_bits16(mci->pdev, I82860_ERRSTS, 0x0003, 0x0003);
+ i82860_get_error_info(mci, &discard); /* clear counters */
if (edac_mc_add_mc(mci)) {
debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
u32 drc_chan; /* Number of channels 0=1chan,1=2chan */
u32 nr_chans;
u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
+ struct i82875p_error_info discard;
debugf0("%s()\n", __func__);
csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
}
- /* clear counters */
- pci_write_bits16(mci->pdev, I82875P_ERRSTS, 0x0081, 0x0081);
+ i82875p_get_error_info(mci, &discard); /* clear counters */
if (edac_mc_add_mc(mci)) {
debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
u32 scrub_disabled;
u32 sdram_refresh_rate;
u32 row_high_limit_last = 0;
- u32 eap_init_bits;
+ struct r82600_error_info discard;
debugf0("%s()\n", __func__);
row_high_limit_last = row_high_limit;
}
- /* clear counters */
- /* FIXME should we? */
+ r82600_get_error_info(mci, &discard); /* clear counters */
if (edac_mc_add_mc(mci)) {
debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
/* get this far and it's successful */
- /* Clear error flags to allow next error to be reported [p.62] */
- /* Test systems seem to always have the UE flag raised on boot */
-
- eap_init_bits = BIT(0) & BIT(1);
if (disable_hardware_scrub) {
- eap_init_bits |= BIT(31);
debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n",
__func__);
+ pci_write_bits32(mci->pdev, R82600_EAP, BIT(31), BIT(31));
}
- pci_write_bits32(mci->pdev, R82600_EAP, eap_init_bits,
- eap_init_bits);
-
debugf3("%s(): success\n", __func__);
return 0;