clk: hi3660: fix wrong parent name of clk_mux_sysbus
authorChen Jun <chenjun14@huawei.com>
Fri, 26 May 2017 07:38:19 +0000 (15:38 +0800)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 20 Jun 2017 01:00:20 +0000 (18:00 -0700)
Parent name of clk_mux_sysbus is not correct. This patch fixes it.

Signed-off-by: Chen Jun <chenjun14@huawei.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/hisilicon/clk-hi3660.c

index 3bc5efba5fad7dcf2945621f0f22e4dc3c13ccba..c5044e5e1fe671d94381702452a96ffe914ad74a 100644 (file)
@@ -205,6 +205,8 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_clks[] = {
          "clk_gate_ufs_tcxo_en", CLK_SET_RATE_PARENT, 0x420, 14, 0, },
 };
 
+static const char *const
+clk_mux_sysbus_p[] = {"clk_ppll1", "clk_ppll0"};
 static const char *const
 clk_mux_sdio_sys_p[] = {"clk_factor_mmc", "clk_div_sdio",};
 static const char *const
@@ -239,8 +241,8 @@ static const char *const
 clk_mux_i2c_p[] = {"clkin_sys", "clk_div_i2c",};
 
 static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = {
-       { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sdio_sys_p,
-         ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT, 0xac, 0, 1,
+       { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p,
+         ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT, 0xac, 0, 1,
          CLK_MUX_HIWORD_MASK, },
        { HI3660_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
          ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, 0xac, 2, 1,