clk: uniphier: add core support code for UniPhier clock driver

This includes UniPhier clock driver code, except SoC-specific
data arrays.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/MAINTAINERS b/MAINTAINERS
index d695e65cb168ba6ffe91ddf99746e592162fb753..42ec61c5eaa6cd460e58327ef2436c6e2814ebc4 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1828,6 +1828,7 @@ F:        arch/arm/mach-uniphier/
 F:     arch/arm/mm/cache-uniphier.c
 F:     arch/arm64/boot/dts/socionext/
 F:     drivers/bus/uniphier-system-bus.c
+F:     drivers/clk/uniphier/
 F:     drivers/i2c/busses/i2c-uniphier*
 F:     drivers/pinctrl/uniphier/
 F:     drivers/tty/serial/8250/8250_uniphier.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index bf7d540d696563034f62d2ceb7569b195d2109ab..6a8ac04bedebdf13c2a2d1ff9c6e4543d7cc792b 100644 (file)
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -209,5 +209,6 @@ source "drivers/clk/samsung/Kconfig"
 source "drivers/clk/sunxi-ng/Kconfig"
 source "drivers/clk/tegra/Kconfig"
 source "drivers/clk/ti/Kconfig"
+source "drivers/clk/uniphier/Kconfig"
 
 endmenu

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e775a836247c7e632178568bbb7671200211c333..8264d81af5a9d2e73f6386dc3c088b243e5eaa57 100644 (file)
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_ARCH_SUNXI)              += sunxi/
 obj-$(CONFIG_ARCH_SUNXI)               += sunxi-ng/
 obj-$(CONFIG_ARCH_TEGRA)               += tegra/
 obj-y                                  += ti/
+obj-$(CONFIG_CLK_UNIPHIER)             += uniphier/
 obj-$(CONFIG_ARCH_U8500)               += ux500/
 obj-$(CONFIG_COMMON_CLK_VERSATILE)     += versatile/
 obj-$(CONFIG_X86)                      += x86/

diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
new file mode 100644 (file)
index 0000000..5512377
--- /dev/null
+++ b/drivers/clk/uniphier/Kconfig
@@ -0,0 +1,9 @@
+config CLK_UNIPHIER
+       bool "Clock driver for UniPhier SoCs"
+       depends on ARCH_UNIPHIER || COMPILE_TEST
+       depends on OF && MFD_SYSCON
+       default ARCH_UNIPHIER
+       help
+         Support for clock controllers on UniPhier SoCs.
+         Say Y if you want to control clocks provided by System Control
+         block, Media I/O block, Peripheral Block.

diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
new file mode 100644 (file)
index 0000000..88a28ca
--- /dev/null
+++ b/drivers/clk/uniphier/Makefile
@@ -0,0 +1,5 @@
+obj-y  += clk-uniphier-core.o
+obj-y  += clk-uniphier-fixed-factor.o
+obj-y  += clk-uniphier-fixed-rate.o
+obj-y  += clk-uniphier-gate.o
+obj-y  += clk-uniphier-mux.o

diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
new file mode 100644 (file)
index 0000000..a6e2a94
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-uniphier.h"
+
+static struct clk_hw *uniphier_clk_register(struct device *dev,
+                                           struct regmap *regmap,
+                                       const struct uniphier_clk_data *data)
+{
+       switch (data->type) {
+       case UNIPHIER_CLK_TYPE_FIXED_FACTOR:
+               return uniphier_clk_register_fixed_factor(dev, data->name,
+                                                         &data->data.factor);
+       case UNIPHIER_CLK_TYPE_FIXED_RATE:
+               return uniphier_clk_register_fixed_rate(dev, data->name,
+                                                       &data->data.rate);
+       case UNIPHIER_CLK_TYPE_GATE:
+               return uniphier_clk_register_gate(dev, regmap, data->name,
+                                                 &data->data.gate);
+       case UNIPHIER_CLK_TYPE_MUX:
+               return uniphier_clk_register_mux(dev, regmap, data->name,
+                                                &data->data.mux);
+       default:
+               dev_err(dev, "unsupported clock type\n");
+               return ERR_PTR(-EINVAL);
+       }
+}
+
+static int uniphier_clk_probe(struct platform_device *pdev)
+{
+       struct device *dev = &pdev->dev;
+       struct clk_hw_onecell_data *hw_data;
+       const struct uniphier_clk_data *p, *data;
+       struct regmap *regmap;
+       struct device_node *parent;
+       int clk_num = 0;
+
+       data = of_device_get_match_data(dev);
+       if (WARN_ON(!data))
+               return -EINVAL;
+
+       parent = of_get_parent(dev->of_node); /* parent should be syscon node */
+       regmap = syscon_node_to_regmap(parent);
+       of_node_put(parent);
+       if (IS_ERR(regmap)) {
+               dev_err(dev, "failed to get regmap (error %ld)\n",
+                       PTR_ERR(regmap));
+               return PTR_ERR(regmap);
+       }
+
+       for (p = data; p->name; p++)
+               clk_num = max(clk_num, p->idx + 1);
+
+       hw_data = devm_kzalloc(dev,
+                       sizeof(*hw_data) + clk_num * sizeof(struct clk_hw *),
+                       GFP_KERNEL);
+       if (!hw_data)
+               return -ENOMEM;
+
+       hw_data->num = clk_num;
+
+       /* avoid returning NULL for unused idx */
+       for (; clk_num >= 0; clk_num--)
+               hw_data->hws[clk_num] = ERR_PTR(-EINVAL);
+
+       for (p = data; p->name; p++) {
+               struct clk_hw *hw;
+
+               dev_dbg(dev, "register %s (index=%d)\n", p->name, p->idx);
+               hw = uniphier_clk_register(dev, regmap, p);
+               if (IS_ERR(hw)) {
+                       dev_err(dev, "failed to register %s (error %ld)\n",
+                               p->name, PTR_ERR(hw));
+                       return PTR_ERR(hw);
+               }
+
+               if (p->idx >= 0)
+                       hw_data->hws[p->idx] = hw;
+       }
+
+       return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
+                                     hw_data);
+}
+
+static int uniphier_clk_remove(struct platform_device *pdev)
+{
+       of_clk_del_provider(pdev->dev.of_node);
+
+       return 0;
+}
+
+static const struct of_device_id uniphier_clk_match[] = {
+       { /* sentinel */ }
+};
+
+static struct platform_driver uniphier_clk_driver = {
+       .probe = uniphier_clk_probe,
+       .remove = uniphier_clk_remove,
+       .driver = {
+               .name = "uniphier-clk",
+               .of_match_table = uniphier_clk_match,
+       },
+};
+builtin_platform_driver(uniphier_clk_driver);

diff --git a/drivers/clk/uniphier/clk-uniphier-fixed-factor.c b/drivers/clk/uniphier/clk-uniphier-fixed-factor.c
new file mode 100644 (file)
index 0000000..da2d9f4
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-fixed-factor.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+
+#include "clk-uniphier.h"
+
+struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev,
+                                                 const char *name,
+                       const struct uniphier_clk_fixed_factor_data *data)
+{
+       struct clk_fixed_factor *fix;
+       struct clk_init_data init;
+       int ret;
+
+       fix = devm_kzalloc(dev, sizeof(*fix), GFP_KERNEL);
+       if (!fix)
+               return ERR_PTR(-ENOMEM);
+
+       init.name = name;
+       init.ops = &clk_fixed_factor_ops;
+       init.flags = data->parent_name ? CLK_SET_RATE_PARENT : 0;
+       init.parent_names = data->parent_name ? &data->parent_name : NULL;
+       init.num_parents = data->parent_name ? 1 : 0;
+
+       fix->mult = data->mult;
+       fix->div = data->div;
+       fix->hw.init = &init;
+
+       ret = devm_clk_hw_register(dev, &fix->hw);
+       if (ret)
+               return ERR_PTR(ret);
+
+       return &fix->hw;
+}

diff --git a/drivers/clk/uniphier/clk-uniphier-fixed-rate.c b/drivers/clk/uniphier/clk-uniphier-fixed-rate.c
new file mode 100644 (file)
index 0000000..0ad0d46
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-fixed-rate.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+
+#include "clk-uniphier.h"
+
+struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev,
+                                               const char *name,
+                               const struct uniphier_clk_fixed_rate_data *data)
+{
+       struct clk_fixed_rate *fixed;
+       struct clk_init_data init;
+       int ret;
+
+       /* allocate fixed-rate clock */
+       fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
+       if (!fixed)
+               return ERR_PTR(-ENOMEM);
+
+       init.name = name;
+       init.ops = &clk_fixed_rate_ops;
+       init.parent_names = NULL;
+       init.num_parents = 0;
+
+       fixed->fixed_rate = data->fixed_rate;
+       fixed->hw.init = &init;
+
+       ret = devm_clk_hw_register(dev, &fixed->hw);
+       if (ret)
+               return ERR_PTR(ret);
+
+       return &fixed->hw;
+}

diff --git a/drivers/clk/uniphier/clk-uniphier-gate.c b/drivers/clk/uniphier/clk-uniphier-gate.c
new file mode 100644 (file)
index 0000000..49142d4
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-gate.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/regmap.h>
+
+#include "clk-uniphier.h"
+
+struct uniphier_clk_gate {
+       struct clk_hw hw;
+       struct regmap *regmap;
+       unsigned int reg;
+       unsigned int bit;
+};
+
+#define to_uniphier_clk_gate(_hw) \
+                               container_of(_hw, struct uniphier_clk_gate, hw)
+
+static int uniphier_clk_gate_endisable(struct clk_hw *hw, int enable)
+{
+       struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
+
+       return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit),
+                                enable ? BIT(gate->bit) : 0);
+}
+
+static int uniphier_clk_gate_enable(struct clk_hw *hw)
+{
+       return uniphier_clk_gate_endisable(hw, 1);
+}
+
+static void uniphier_clk_gate_disable(struct clk_hw *hw)
+{
+       if (uniphier_clk_gate_endisable(hw, 0) < 0)
+               pr_warn("failed to disable clk\n");
+}
+
+static int uniphier_clk_gate_is_enabled(struct clk_hw *hw)
+{
+       struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
+       unsigned int val;
+
+       if (regmap_read(gate->regmap, gate->reg, &val) < 0)
+               pr_warn("is_enabled() may return wrong result\n");
+
+       return !!(val & BIT(gate->bit));
+}
+
+static const struct clk_ops uniphier_clk_gate_ops = {
+       .enable = uniphier_clk_gate_enable,
+       .disable = uniphier_clk_gate_disable,
+       .is_enabled = uniphier_clk_gate_is_enabled,
+};
+
+struct clk_hw *uniphier_clk_register_gate(struct device *dev,
+                                         struct regmap *regmap,
+                                         const char *name,
+                               const struct uniphier_clk_gate_data *data)
+{
+       struct uniphier_clk_gate *gate;
+       struct clk_init_data init;
+       int ret;
+
+       gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
+       if (!gate)
+               return ERR_PTR(-ENOMEM);
+
+       init.name = name;
+       init.ops = &uniphier_clk_gate_ops;
+       init.flags = data->parent_name ? CLK_SET_RATE_PARENT : 0;
+       init.parent_names = data->parent_name ? &data->parent_name : NULL;
+       init.num_parents = data->parent_name ? 1 : 0;
+
+       gate->regmap = regmap;
+       gate->reg = data->reg;
+       gate->bit = data->bit;
+       gate->hw.init = &init;
+
+       ret = devm_clk_hw_register(dev, &gate->hw);
+       if (ret)
+               return ERR_PTR(ret);
+
+       return &gate->hw;
+}

diff --git a/drivers/clk/uniphier/clk-uniphier-mux.c b/drivers/clk/uniphier/clk-uniphier-mux.c
new file mode 100644 (file)
index 0000000..15a2f2c
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-mux.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/regmap.h>
+
+#include "clk-uniphier.h"
+
+struct uniphier_clk_mux {
+       struct clk_hw hw;
+       struct regmap *regmap;
+       unsigned int reg;
+       const unsigned int *masks;
+       const unsigned int *vals;
+};
+
+#define to_uniphier_clk_mux(_hw) container_of(_hw, struct uniphier_clk_mux, hw)
+
+static int uniphier_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+       struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
+
+       return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index],
+                                mux->vals[index]);
+}
+
+static u8 uniphier_clk_mux_get_parent(struct clk_hw *hw)
+{
+       struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
+       int num_parents = clk_hw_get_num_parents(hw);
+       int ret;
+       u32 val;
+       u8 i;
+
+       ret = regmap_read(mux->regmap, mux->reg, &val);
+       if (ret)
+               return ret;
+
+       for (i = 0; i < num_parents; i++)
+               if ((mux->masks[i] & val) == mux->vals[i])
+                       return i;
+
+       return -EINVAL;
+}
+
+static const struct clk_ops uniphier_clk_mux_ops = {
+       .determine_rate = __clk_mux_determine_rate,
+       .set_parent = uniphier_clk_mux_set_parent,
+       .get_parent = uniphier_clk_mux_get_parent,
+};
+
+struct clk_hw *uniphier_clk_register_mux(struct device *dev,
+                                        struct regmap *regmap,
+                                        const char *name,
+                               const struct uniphier_clk_mux_data *data)
+{
+       struct uniphier_clk_mux *mux;
+       struct clk_init_data init;
+       int ret;
+
+       mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+       if (!mux)
+               return ERR_PTR(-ENOMEM);
+
+       init.name = name;
+       init.ops = &uniphier_clk_mux_ops;
+       init.flags = CLK_SET_RATE_PARENT;
+       init.parent_names = data->parent_names;
+       init.num_parents = data->num_parents,
+
+       mux->regmap = regmap;
+       mux->reg = data->reg;
+       mux->masks = data->masks;
+       mux->vals = data->vals;
+       mux->hw.init = &init;
+
+       ret = devm_clk_hw_register(dev, &mux->hw);
+       if (ret)
+               return ERR_PTR(ret);
+
+       return &mux->hw;
+}

diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h
new file mode 100644 (file)
index 0000000..3e354e9
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CLK_UNIPHIER_H__
+#define __CLK_UNIPHIER_H__
+
+struct clk_hw;
+struct device;
+struct regmap;
+
+#define UNIPHIER_CLK_MUX_MAX_PARENTS   8
+
+enum uniphier_clk_type {
+       UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+       UNIPHIER_CLK_TYPE_FIXED_RATE,
+       UNIPHIER_CLK_TYPE_GATE,
+       UNIPHIER_CLK_TYPE_MUX,
+};
+
+struct uniphier_clk_fixed_factor_data {
+       const char *parent_name;
+       unsigned int mult;
+       unsigned int div;
+};
+
+struct uniphier_clk_fixed_rate_data {
+       unsigned long fixed_rate;
+};
+
+struct uniphier_clk_gate_data {
+       const char *parent_name;
+       unsigned int reg;
+       unsigned int bit;
+};
+
+struct uniphier_clk_mux_data {
+       const char *parent_names[UNIPHIER_CLK_MUX_MAX_PARENTS];
+       unsigned int num_parents;
+       unsigned int reg;
+       unsigned int masks[UNIPHIER_CLK_MUX_MAX_PARENTS];
+       unsigned int vals[UNIPHIER_CLK_MUX_MAX_PARENTS];
+};
+
+struct uniphier_clk_data {
+       const char *name;
+       enum uniphier_clk_type type;
+       int idx;
+       union {
+               struct uniphier_clk_fixed_factor_data factor;
+               struct uniphier_clk_fixed_rate_data rate;
+               struct uniphier_clk_gate_data gate;
+               struct uniphier_clk_mux_data mux;
+       } data;
+};
+
+#define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div) \
+       {                                                       \
+               .name = (_name),                                \
+               .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,         \
+               .idx = (_idx),                                  \
+               .data.factor = {                                \
+                       .parent_name = (_parent),               \
+                       .mult = (_mult),                        \
+                       .div = (_div),                          \
+               },                                              \
+       }
+
+
+#define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit)    \
+       {                                                       \
+               .name = (_name),                                \
+               .type = UNIPHIER_CLK_TYPE_GATE,                 \
+               .idx = (_idx),                                  \
+               .data.gate = {                                  \
+                       .parent_name = (_parent),               \
+                       .reg = (_reg),                          \
+                       .bit = (_bit),                          \
+               },                                              \
+       }
+
+
+struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev,
+                                                 const char *name,
+                       const struct uniphier_clk_fixed_factor_data *data);
+struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev,
+                                               const char *name,
+                       const struct uniphier_clk_fixed_rate_data *data);
+struct clk_hw *uniphier_clk_register_gate(struct device *dev,
+                                         struct regmap *regmap,
+                                         const char *name,
+                               const struct uniphier_clk_gate_data *data);
+struct clk_hw *uniphier_clk_register_mux(struct device *dev,
+                                        struct regmap *regmap,
+                                        const char *name,
+                               const struct uniphier_clk_mux_data *data);
+
+#endif /* __CLK_UNIPHIER_H__ */