drm/i915: Ignore skl+ for debugfs/i915_sr_status

There is no easily digestible single self-refresh status bit, so don't
report one for debugfs/i915_sr_status on gen9+. For the moment this
avoids a read of the non-existent WM1_LP_ILK register.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170309142049.16033-1-chris@chris-wilson.co.uk
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fd0aa29e0c3b9a6b22d1f46181b70a00115f1cda..115433d46477aebaac679623df4a0a56cf4100ed 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1749,7 +1749,9 @@ static int i915_sr_status(struct seq_file *m, void *unused)
        intel_runtime_pm_get(dev_priv);
        intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 
-       if (HAS_PCH_SPLIT(dev_priv))
+       if (INTEL_GEN(dev_priv) >= 9)
+               /* no global SR status; inspect per-plane WM */;
+       else if (HAS_PCH_SPLIT(dev_priv))
                sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
        else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
                 IS_I945G(dev_priv) || IS_I945GM(dev_priv))