#define m5206sim_h
/****************************************************************************/
-#define CPU_NAME "COLDFIRE(m5206)"
+#define CPU_NAME "COLDFIRE(m5206)"
+#define CPU_INSTR_PER_JIFFY 3
/*
* Define the 5206 SIM register set addresses.
#define m520xsim_h
/****************************************************************************/
-#define CPU_NAME "COLDFIRE(m520x)"
+#define CPU_NAME "COLDFIRE(m520x)"
+#define CPU_INSTR_PER_JIFFY 3
/*
* Define the 520x SIM register set addresses.
#define m523xsim_h
/****************************************************************************/
-#define CPU_NAME "COLDFIRE(m523x)"
+#define CPU_NAME "COLDFIRE(m523x)"
+#define CPU_INSTR_PER_JIFFY 3
/*
* Define the 523x SIM register set addresses.
#define m5249sim_h
/****************************************************************************/
-#define CPU_NAME "COLDFIRE(m5249)"
+#define CPU_NAME "COLDFIRE(m5249)"
+#define CPU_INSTR_PER_JIFFY 3
/*
* Define the 5249 SIM register set addresses.
#define m5272sim_h
/****************************************************************************/
-#define CPU_NAME "COLDFIRE(m5272)"
+#define CPU_NAME "COLDFIRE(m5272)"
+#define CPU_INSTR_PER_JIFFY 3
/*
* Define the 5272 SIM register set addresses.
#define m527xsim_h
/****************************************************************************/
-#define CPU_NAME "COLDFIRE(m527x)"
+#define CPU_NAME "COLDFIRE(m527x)"
+#define CPU_INSTR_PER_JIFFY 3
/*
#define m528xsim_h
/****************************************************************************/
-#define CPU_NAME "COLDFIRE(m528x)"
+#define CPU_NAME "COLDFIRE(m528x)"
+#define CPU_INSTR_PER_JIFFY 3
/*
* Define the 5280/5282 SIM register set addresses.
#define m5307sim_h
/****************************************************************************/
-#define CPU_NAME "COLDFIRE(m5307)"
+#define CPU_NAME "COLDFIRE(m5307)"
+#define CPU_INSTR_PER_JIFFY 3
/*
* Define the 5307 SIM register set addresses.
#define m532xsim_h
/****************************************************************************/
-#define CPU_NAME "COLDFIRE(m532x)"
+#define CPU_NAME "COLDFIRE(m532x)"
+#define CPU_INSTR_PER_JIFFY 3
#define MCF_REG32(x) (*(volatile unsigned long *)(x))
#define MCF_REG16(x) (*(volatile unsigned short *)(x))
#define m5407sim_h
/****************************************************************************/
-#define CPU_NAME "COLDFIRE(m5407)"
+#define CPU_NAME "COLDFIRE(m5407)"
+#define CPU_INSTR_PER_JIFFY 3
/*
* Define the 5407 SIM register set addresses.
#ifndef m54xxsim_h
#define m54xxsim_h
-#define CPU_NAME "COLDFIRE(m54xx)"
+#define CPU_NAME "COLDFIRE(m54xx)"
+#define CPU_INSTR_PER_JIFFY 2
-#define MCFINT_VECBASE 64
+#define MCFINT_VECBASE 64
/*
* Interrupt Controller Registers
#ifdef CONFIG_M68360
#define CPU_NAME "MC68360"
#endif
-/*
- * The ColdFire CPU names are defined in their headers.
- */
#ifndef CPU_NAME
#define CPU_NAME "UNKNOWN"
#endif
+/*
+ * Different cores have different instruction execution timings.
+ * The old/traditional 68000 cores are basically all the same, at 16.
+ * The ColdFire cores vary a little, their values are defined in their
+ * headers. We default to the standard 68000 value here.
+ */
+#ifndef CPU_INSTR_PER_JIFFY
+#define CPU_INSTR_PER_JIFFY 16
+#endif
+
extern int _stext, _etext, _sdata, _edata, _sbss, _ebss, _end;
extern int _ramstart, _ramend;
cpu = CPU_NAME;
mmu = "none";
fpu = "none";
-
-#ifdef CONFIG_COLDFIRE
- clockfreq = (loops_per_jiffy * HZ) * 3;
-#else
- clockfreq = (loops_per_jiffy * HZ) * 16;
-#endif
+ clockfreq = (loops_per_jiffy * HZ) * CPU_INSTR_PER_JIFFY;
seq_printf(m, "CPU:\t\t%s\n"
"MMU:\t\t%s\n"