#include "prcm44xx.h"
#include <plat/clock.h>
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include "clockdomain.h"
#include <plat/prcm.h>
#include <linux/init.h>
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/prcm.h>
#include <plat/irqs.h>
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include "clockdomain.h"
#include <plat/serial.h>
#include "io.h"
#include <plat/omap-pm.h>
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include "clockdomain.h"
#include <plat/omap_hwmod.h>
#include <plat/common.h>
#include <plat/cpu.h>
#include "clockdomain.h"
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include <plat/clock.h>
#include <plat/omap_hwmod.h>
#include <plat/prcm.h>
#include <plat/clock.h>
#include <plat/board.h>
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include "clockdomain.h"
#include <plat/dmtimer.h>
#include <plat/omap_device.h>
#include <plat/common.h>
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include "clockdomain.h"
static struct omap_device_pm_latency *pm_lats;
#ifndef __ARCH_ARM_MACH_OMAP2_PM_H
#define __ARCH_ARM_MACH_OMAP2_PM_H
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
extern void *omap3_secure_ram_storage;
extern void omap3_pm_off_mode_enable(int);
#include "pm.h"
#include "control.h"
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include "clockdomain.h"
#ifdef CONFIG_SUSPEND
l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
- omap2_gpio_prepare_for_idle(PWRDM_POWER_RET);
+ omap2_gpio_prepare_for_idle(0);
if (omap2_pm_debug) {
omap2_pm_dump(0, 0, 0);
#include <plat/sram.h>
#include "clockdomain.h"
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include <plat/serial.h>
#include <plat/sdrc.h>
#include <plat/prcm.h>
int mpu_next_state = PWRDM_POWER_ON;
int per_next_state = PWRDM_POWER_ON;
int core_next_state = PWRDM_POWER_ON;
+ int per_going_off;
int core_prev_state, per_prev_state;
u32 sdrc_pwr = 0;
/* PER */
if (per_next_state < PWRDM_POWER_ON) {
+ per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
omap_uart_prepare_idle(2);
omap_uart_prepare_idle(3);
- omap2_gpio_prepare_for_idle(per_next_state);
+ omap2_gpio_prepare_for_idle(per_going_off);
if (per_next_state == PWRDM_POWER_OFF)
omap3_per_save_context();
}
#include <linux/err.h>
#include <linux/slab.h>
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include <mach/omap4-common.h>
struct power_state {
#include "cm-regbits-44xx.h"
#include "prm-regbits-34xx.h"
#include "prm-regbits-44xx.h"
-#include "powerdomains.h"
/*
* OMAP3 and OMAP4 specific register bit initialisations
#include "prm44xx.h"
#include <plat/cpu.h>
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include "clockdomain.h"
#include <plat/prcm.h>
--- /dev/null
+/*
+ * OMAP2/3/4 powerdomain control
+ *
+ * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This should be moved to the mach-omap2/ directory at the earliest
+ * opportunity.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
+#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
+
+#include <linux/types.h>
+#include <linux/list.h>
+
+#include <linux/atomic.h>
+
+#include <plat/cpu.h>
+
+/* Powerdomain basic power states */
+#define PWRDM_POWER_OFF 0x0
+#define PWRDM_POWER_RET 0x1
+#define PWRDM_POWER_INACTIVE 0x2
+#define PWRDM_POWER_ON 0x3
+
+#define PWRDM_MAX_PWRSTS 4
+
+/* Powerdomain allowable state bitfields */
+#define PWRSTS_ON (1 << PWRDM_POWER_ON)
+#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
+#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
+ (1 << PWRDM_POWER_ON))
+
+#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
+ (1 << PWRDM_POWER_RET))
+
+#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \
+ (1 << PWRDM_POWER_ON))
+
+#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
+
+
+/* Powerdomain flags */
+#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
+#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
+ * in MEM bank 1 position. This is
+ * true for OMAP3430
+ */
+#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
+ * support to transition from a
+ * sleep state to a lower sleep
+ * state without waking up the
+ * powerdomain
+ */
+
+/*
+ * Number of memory banks that are power-controllable. On OMAP4430, the
+ * maximum is 5.
+ */
+#define PWRDM_MAX_MEM_BANKS 5
+
+/*
+ * Maximum number of clockdomains that can be associated with a powerdomain.
+ * CORE powerdomain on OMAP4 is the worst case
+ */
+#define PWRDM_MAX_CLKDMS 9
+
+/* XXX A completely arbitrary number. What is reasonable here? */
+#define PWRDM_TRANSITION_BAILOUT 100000
+
+struct clockdomain;
+struct powerdomain;
+
+/**
+ * struct powerdomain - OMAP powerdomain
+ * @name: Powerdomain name
+ * @omap_chip: represents the OMAP chip types containing this pwrdm
+ * @prcm_offs: the address offset from CM_BASE/PRM_BASE
+ * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
+ * @pwrsts: Possible powerdomain power states
+ * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
+ * @flags: Powerdomain flags
+ * @banks: Number of software-controllable memory banks in this powerdomain
+ * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
+ * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
+ * @pwrdm_clkdms: Clockdomains in this powerdomain
+ * @node: list_head linking all powerdomains
+ * @state:
+ * @state_counter:
+ * @timer:
+ * @state_timer:
+ *
+ * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
+ */
+struct powerdomain {
+ const char *name;
+ const struct omap_chip_id omap_chip;
+ const s16 prcm_offs;
+ const u8 pwrsts;
+ const u8 pwrsts_logic_ret;
+ const u8 flags;
+ const u8 banks;
+ const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
+ const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
+ const u8 prcm_partition;
+ struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
+ struct list_head node;
+ int state;
+ unsigned state_counter[PWRDM_MAX_PWRSTS];
+ unsigned ret_logic_off_counter;
+ unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
+
+#ifdef CONFIG_PM_DEBUG
+ s64 timer;
+ s64 state_timer[PWRDM_MAX_PWRSTS];
+#endif
+};
+
+/**
+ * struct pwrdm_ops - Arch specfic function implementations
+ * @pwrdm_set_next_pwrst: Set the target power state for a pd
+ * @pwrdm_read_next_pwrst: Read the target power state set for a pd
+ * @pwrdm_read_pwrst: Read the current power state of a pd
+ * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
+ * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
+ * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
+ * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
+ * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
+ * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
+ * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
+ * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
+ * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
+ * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
+ * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
+ * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
+ * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
+ * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
+ * @pwrdm_wait_transition: Wait for a pd state transition to complete
+ */
+struct pwrdm_ops {
+ int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
+ int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
+ int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
+ int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
+ int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
+ int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+ int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+ int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
+ int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
+ int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
+ int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
+ int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
+ int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
+ int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
+ int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
+ int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
+ int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
+ int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
+};
+
+void pwrdm_fw_init(void);
+void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs);
+
+struct powerdomain *pwrdm_lookup(const char *name);
+
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+ void *user);
+int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
+ void *user);
+
+int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
+int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
+int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
+ int (*fn)(struct powerdomain *pwrdm,
+ struct clockdomain *clkdm));
+
+int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
+
+int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
+int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
+int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
+
+int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
+int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+
+int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
+int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
+int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
+int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
+
+int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
+int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
+bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
+
+int pwrdm_wait_transition(struct powerdomain *pwrdm);
+
+int pwrdm_state_switch(struct powerdomain *pwrdm);
+int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
+int pwrdm_pre_transition(void);
+int pwrdm_post_transition(void);
+int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
+
+extern void omap2xxx_powerdomains_init(void);
+extern void omap3xxx_powerdomains_init(void);
+extern void omap44xx_powerdomains_init(void);
+
+extern struct pwrdm_ops omap2_pwrdm_operations;
+extern struct pwrdm_ops omap3_pwrdm_operations;
+extern struct pwrdm_ops omap4_pwrdm_operations;
+
+/* Common Internal functions used across OMAP rev's */
+extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
+extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
+extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
+
+extern struct powerdomain wkup_omap2_pwrdm;
+extern struct powerdomain gfx_omap2_pwrdm;
+
+
+#endif
#include <plat/prcm.h>
+#include "powerdomain.h"
#include "prm-regbits-34xx.h"
-#include "powerdomains.h"
#include "prm.h"
#include "prm-regbits-24xx.h"
#include "prm-regbits-34xx.h"
#include <linux/errno.h>
#include <linux/delay.h>
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include <plat/prcm.h>
#include "prm2xxx_3xxx.h"
#include "prm44xx.h"
#include "prminst44xx.h"
#include "prm-regbits-44xx.h"
-#include "powerdomains.h"
static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
{
+++ /dev/null
-/*
- * OMAP2+ powerdomain prototypes
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- *
- * Rajendra Nayak <rnayak@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS_H
-#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS_H
-
-#include <plat/powerdomain.h>
-
-extern struct pwrdm_ops omap2_pwrdm_operations;
-extern struct pwrdm_ops omap3_pwrdm_operations;
-extern struct pwrdm_ops omap4_pwrdm_operations;
-
-/* Common Internal functions used across OMAP rev's */
-extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
-extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
-extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
-
-extern struct powerdomain wkup_omap2_pwrdm;
-extern struct powerdomain gfx_omap2_pwrdm;
-
-#endif
* address offset is different between the C55 and C64 DSPs.
*/
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include "prcm-common.h"
#include "prm.h"
-#include "powerdomains.h"
-
/* OMAP2/3-common powerdomains */
/*
#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H
#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
extern struct powerdomain gfx_omap2_pwrdm;
extern struct powerdomain wkup_omap2_pwrdm;
#include <linux/kernel.h>
#include <linux/init.h>
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include "powerdomains2xxx_3xxx_data.h"
-#include "powerdomains.h"
#include "prcm-common.h"
#include "prm2xxx_3xxx.h"
#include <linux/kernel.h>
#include <linux/init.h>
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
#include "powerdomains2xxx_3xxx_data.h"
-#include "powerdomains.h"
#include "prcm-common.h"
#include "prm2xxx_3xxx.h"
#include <linux/kernel.h>
#include <linux/init.h>
-#include <plat/powerdomain.h>
-#include "powerdomains.h"
+#include "powerdomain.h"
#include "prcm-common.h"
#include "prcm44xx.h"
#include <mach/irqs.h>
#include <mach/gpio.h>
#include <asm/mach/irq.h>
-#include <plat/powerdomain.h>
/*
* OMAP1510 GPIO registers
static int workaround_enabled;
-void omap2_gpio_prepare_for_idle(int power_state)
+void omap2_gpio_prepare_for_idle(int off_mode)
{
int i, c = 0;
int min = 0;
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
clk_disable(bank->dbck);
- if (power_state > PWRDM_POWER_OFF)
+ if (!off_mode)
continue;
/* If going to OFF, remove triggering for all
/* TODO: Analyze removing gpio_bank_count usage from driver code */
extern int gpio_bank_count;
-extern void omap2_gpio_prepare_for_idle(int power_state);
+extern void omap2_gpio_prepare_for_idle(int off_mode);
extern void omap2_gpio_resume_after_idle(void);
extern void omap_set_gpio_debounce(int gpio, int enable);
extern void omap_set_gpio_debounce_time(int gpio, int enable);
#include <linux/clk.h>
#include <linux/opp.h>
-#include "powerdomain.h"
-
/*
* agent_id values for use with omap_pm_set_min_bus_tput():
*
+++ /dev/null
-/*
- * OMAP2/3/4 powerdomain control
- *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
- *
- * Written by Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * XXX This should be moved to the mach-omap2/ directory at the earliest
- * opportunity.
- */
-
-#ifndef ASM_ARM_PLAT_OMAP_INCLUDE_PLAT_POWERDOMAIN
-#define ASM_ARM_PLAT_OMAP_INCLUDE_PLAT_POWERDOMAIN
-
-#include <linux/types.h>
-#include <linux/list.h>
-
-#include <asm/atomic.h>
-
-#include <plat/cpu.h>
-
-/* Powerdomain basic power states */
-#define PWRDM_POWER_OFF 0x0
-#define PWRDM_POWER_RET 0x1
-#define PWRDM_POWER_INACTIVE 0x2
-#define PWRDM_POWER_ON 0x3
-
-#define PWRDM_MAX_PWRSTS 4
-
-/* Powerdomain allowable state bitfields */
-#define PWRSTS_ON (1 << PWRDM_POWER_ON)
-#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
-#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
- (1 << PWRDM_POWER_ON))
-
-#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
- (1 << PWRDM_POWER_RET))
-
-#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \
- (1 << PWRDM_POWER_ON))
-
-#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
-
-
-/* Powerdomain flags */
-#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
-#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
- * in MEM bank 1 position. This is
- * true for OMAP3430
- */
-#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
- * support to transition from a
- * sleep state to a lower sleep
- * state without waking up the
- * powerdomain
- */
-
-/*
- * Number of memory banks that are power-controllable. On OMAP4430, the
- * maximum is 5.
- */
-#define PWRDM_MAX_MEM_BANKS 5
-
-/*
- * Maximum number of clockdomains that can be associated with a powerdomain.
- * CORE powerdomain on OMAP4 is the worst case
- */
-#define PWRDM_MAX_CLKDMS 9
-
-/* XXX A completely arbitrary number. What is reasonable here? */
-#define PWRDM_TRANSITION_BAILOUT 100000
-
-struct clockdomain;
-struct powerdomain;
-
-/**
- * struct powerdomain - OMAP powerdomain
- * @name: Powerdomain name
- * @omap_chip: represents the OMAP chip types containing this pwrdm
- * @prcm_offs: the address offset from CM_BASE/PRM_BASE
- * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
- * @pwrsts: Possible powerdomain power states
- * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
- * @flags: Powerdomain flags
- * @banks: Number of software-controllable memory banks in this powerdomain
- * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
- * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
- * @pwrdm_clkdms: Clockdomains in this powerdomain
- * @node: list_head linking all powerdomains
- * @state:
- * @state_counter:
- * @timer:
- * @state_timer:
- *
- * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
- */
-struct powerdomain {
- const char *name;
- const struct omap_chip_id omap_chip;
- const s16 prcm_offs;
- const u8 pwrsts;
- const u8 pwrsts_logic_ret;
- const u8 flags;
- const u8 banks;
- const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
- const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
- const u8 prcm_partition;
- struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
- struct list_head node;
- int state;
- unsigned state_counter[PWRDM_MAX_PWRSTS];
- unsigned ret_logic_off_counter;
- unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
-
-#ifdef CONFIG_PM_DEBUG
- s64 timer;
- s64 state_timer[PWRDM_MAX_PWRSTS];
-#endif
-};
-
-/**
- * struct pwrdm_ops - Arch specfic function implementations
- * @pwrdm_set_next_pwrst: Set the target power state for a pd
- * @pwrdm_read_next_pwrst: Read the target power state set for a pd
- * @pwrdm_read_pwrst: Read the current power state of a pd
- * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
- * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
- * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
- * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
- * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
- * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
- * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
- * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
- * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
- * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
- * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
- * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
- * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
- * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
- * @pwrdm_wait_transition: Wait for a pd state transition to complete
- */
-struct pwrdm_ops {
- int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
- int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
- int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
- int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
- int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
- int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
- int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
- int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
- int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
- int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
- int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
- int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
- int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
- int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
- int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
- int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
- int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
- int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
-};
-
-void pwrdm_fw_init(void);
-void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs);
-
-struct powerdomain *pwrdm_lookup(const char *name);
-
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
- void *user);
-int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
- void *user);
-
-int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
-int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
-int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
- int (*fn)(struct powerdomain *pwrdm,
- struct clockdomain *clkdm));
-
-int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
-
-int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
-int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
-int pwrdm_read_pwrst(struct powerdomain *pwrdm);
-int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
-int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
-
-int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
-int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
-int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
-
-int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
-int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
-int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
-int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
-int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
-int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
-
-int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
-int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
-bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
-
-int pwrdm_wait_transition(struct powerdomain *pwrdm);
-
-int pwrdm_state_switch(struct powerdomain *pwrdm);
-int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
-int pwrdm_pre_transition(void);
-int pwrdm_post_transition(void);
-int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
-
-extern void omap2xxx_powerdomains_init(void);
-extern void omap3xxx_powerdomains_init(void);
-extern void omap44xx_powerdomains_init(void);
-
-#endif
/* Interface documentation is in mach/omap-pm.h */
#include <plat/omap-pm.h>
-#include <plat/powerdomain.h>
-
/*
* Device-driver-originated constraints (via board-*.c files)
*/
* be removed. No driver should call pwrdm_* or clkdm_* functions
* directly; they should rely on OMAP core code to do this.
*/
-#include <plat/powerdomain.h>
+#include <mach-omap2/powerdomain.h>
#include <mach-omap2/clockdomain.h>
/*
* XXX These mach-omap2/ includes are wrong and should be removed. No
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff