drm/amdgpu: consolidate atom scratch reg handling for hangs
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 21 Oct 2016 19:45:22 +0000 (15:45 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 25 Oct 2016 18:38:56 +0000 (14:38 -0400)
Move from asic specific code to common atom code.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h
drivers/gpu/drm/amd/amdgpu/cik.c
drivers/gpu/drm/amd/amdgpu/vi.c

index 8e6bf548d68907f871952f0109186a03373cdd5f..76cbb1d08bce36e9c5dbbc5209ca491c0142c7b7 100644 (file)
@@ -1784,6 +1784,19 @@ void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
                WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
 }
 
+void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
+                                             bool hung)
+{
+       u32 tmp = RREG32(mmBIOS_SCRATCH_3);
+
+       if (hung)
+               tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
+       else
+               tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
+
+       WREG32(mmBIOS_SCRATCH_3, tmp);
+}
+
 /* Atom needs data in little endian format
  * so swap as appropriate when copying data to
  * or from atom. Note that atom operates on
index 17356151db38a9ca91ed25cf1a3450c91352ba7f..e4afb1652fde3db4338d57ba4d07391df47a04b2 100644 (file)
@@ -206,6 +206,8 @@ void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock);
 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev);
 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev);
 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev);
+void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
+                                             bool hung);
 
 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
index 1b70f8fa42806a8cb65a3f414a8847262a5432d6..302df85893ab599bce0d539c398b6b99a0b75695 100644 (file)
@@ -1189,18 +1189,6 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)
        return r;
 }
 
-static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
-{
-       u32 tmp = RREG32(mmBIOS_SCRATCH_3);
-
-       if (hung)
-               tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
-       else
-               tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
-
-       WREG32(mmBIOS_SCRATCH_3, tmp);
-}
-
 /**
  * cik_asic_reset - soft reset GPU
  *
@@ -1213,11 +1201,12 @@ static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hu
 static int cik_asic_reset(struct amdgpu_device *adev)
 {
        int r;
-       cik_set_bios_scratch_engine_hung(adev, true);
+
+       amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 
        r = cik_gpu_pci_config_reset(adev);
 
-       cik_set_bios_scratch_engine_hung(adev, false);
+       amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 
        return r;
 }
index e33399cd1376c3298874ed8634b81015a7aa9535..25c0a71b257dad65398f33800f75ba5ee111dd1a 100644 (file)
@@ -729,18 +729,6 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
        return -EINVAL;
 }
 
-static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
-{
-       u32 tmp = RREG32(mmBIOS_SCRATCH_3);
-
-       if (hung)
-               tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
-       else
-               tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
-
-       WREG32(mmBIOS_SCRATCH_3, tmp);
-}
-
 /**
  * vi_asic_reset - soft reset GPU
  *
@@ -754,11 +742,11 @@ static int vi_asic_reset(struct amdgpu_device *adev)
 {
        int r;
 
-       vi_set_bios_scratch_engine_hung(adev, true);
+       amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 
        r = vi_gpu_pci_config_reset(adev);
 
-       vi_set_bios_scratch_engine_hung(adev, false);
+       amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 
        return r;
 }