int i;
reg = of_iomap(node, 0);
+ if (!reg) {
+ pr_err("Could not map registers for mux-clk: %s\n",
+ of_node_full_name(node));
+ return NULL;
+ }
i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
if (of_property_read_string(node, "clock-output-names", &clk_name)) {
- pr_warn("%s: could not read clock-output-names for \"%s\"\n",
- __func__, clk_name);
+ pr_err("%s: could not read clock-output-names from \"%s\"\n",
+ __func__, of_node_full_name(node));
goto out_unmap;
}
0, &clk_lock);
if (IS_ERR(clk)) {
- pr_warn("%s: failed to register mux clock %s: %ld\n", __func__,
- clk_name, PTR_ERR(clk));
+ pr_err("%s: failed to register mux clock %s: %ld\n", __func__,
+ clk_name, PTR_ERR(clk));
goto out_unmap;
}
- of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
+ pr_err("%s: failed to add clock provider for %s\n",
+ __func__, clk_name);
+ clk_unregister_divider(clk);
+ goto out_unmap;
+ }
return clk;
-
out_unmap:
iounmap(reg);
return NULL;