clk: sunxi-ng: div: Add support for fixed post-divider
authorPriit Laes <plaes@plaes.org>
Sat, 12 Aug 2017 12:43:50 +0000 (20:43 +0800)
committerChen-Yu Tsai <wens@csie.org>
Mon, 14 Aug 2017 14:31:46 +0000 (22:31 +0800)
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
6 is fixed post-divider.

Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
drivers/clk/sunxi-ng/ccu_div.c
drivers/clk/sunxi-ng/ccu_div.h

index c0e5c10d00910325558203f66f288d1f352ec4ef..baa3cf96507b5285f94768cb12e734076e97cf93 100644 (file)
@@ -21,10 +21,18 @@ static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
 {
        struct ccu_div *cd = data;
 
-       return divider_round_rate_parent(&cd->common.hw, parent,
+       if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+               rate *= cd->fixed_post_div;
+
+       rate = divider_round_rate_parent(&cd->common.hw, parent,
                                         rate, parent_rate,
                                         cd->div.table, cd->div.width,
                                         cd->div.flags);
+
+       if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+               rate /= cd->fixed_post_div;
+
+       return rate;
 }
 
 static void ccu_div_disable(struct clk_hw *hw)
@@ -62,8 +70,13 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
        parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
                                                  parent_rate);
 
-       return divider_recalc_rate(hw, parent_rate, val, cd->div.table,
-                                  cd->div.flags);
+       val = divider_recalc_rate(hw, parent_rate, val, cd->div.table,
+                                 cd->div.flags);
+
+       if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+               val /= cd->fixed_post_div;
+
+       return val;
 }
 
 static int ccu_div_determine_rate(struct clk_hw *hw,
@@ -86,6 +99,9 @@ static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
        parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
                                                  parent_rate);
 
+       if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+               rate *= cd->fixed_post_div;
+
        val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
                              cd->div.flags);
 
index 08d07445120439430abb5b57427470ee419d7965..f3a5028dcd147eabd70c69f73e38c6e5bc52bf32 100644 (file)
@@ -86,9 +86,10 @@ struct ccu_div_internal {
 struct ccu_div {
        u32                     enable;
 
-       struct ccu_div_internal         div;
+       struct ccu_div_internal div;
        struct ccu_mux_internal mux;
        struct ccu_common       common;
+       unsigned int            fixed_post_div;
 };
 
 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg,   \