drm/i915: Optimize gen8_enable|disable_vblank functions
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 7 Nov 2013 10:05:45 +0000 (11:05 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 8 Nov 2013 17:10:13 +0000 (18:10 +0100)
Let's cache the IMR value like on other platforms. This is needed to
implement the underrun reporting since then we'll have two places that
change the same register at runtime.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_irq.c

index a06de99ed3fa4912051db148bbab7a84b943796c..9ea0df2c710995dde36be53124fed81caf35eefa 100644 (file)
@@ -2203,17 +2203,14 @@ static int gen8_enable_vblank(struct drm_device *dev, int pipe)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        unsigned long irqflags;
-       uint32_t imr;
 
        if (!i915_pipe_enabled(dev, pipe))
                return -EINVAL;
 
        spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-       imr = I915_READ(GEN8_DE_PIPE_IMR(pipe));
-       if ((imr & GEN8_PIPE_VBLANK) == 1) {
-               I915_WRITE(GEN8_DE_PIPE_IMR(pipe), imr & ~GEN8_PIPE_VBLANK);
-               POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
-       }
+       dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
+       I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+       POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
        spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
        return 0;
 }
@@ -2270,17 +2267,14 @@ static void gen8_disable_vblank(struct drm_device *dev, int pipe)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        unsigned long irqflags;
-       uint32_t imr;
 
        if (!i915_pipe_enabled(dev, pipe))
                return;
 
        spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-       imr = I915_READ(GEN8_DE_PIPE_IMR(pipe));
-       if ((imr & GEN8_PIPE_VBLANK) == 0) {
-               I915_WRITE(GEN8_DE_PIPE_IMR(pipe), imr | GEN8_PIPE_VBLANK);
-               POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
-       }
+       dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
+       I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
+       POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
        spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }