MIPS: Alchemy: use runtime cpu detection in GPIO code.

Remove the cpu subtype cpp macros in favor of runtime detection,
to improve compile coverage of the alchemy common code.
(Increases kernel size by 700 bytes).

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/699/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib-au1000.c
index 1bfa91f939f45721cbb3239a40bef3c72fc8d70b..c8e1a94d4a95d8c3c308c7fc0d946b78acdca064 100644 (file)
--- a/arch/mips/alchemy/common/gpiolib-au1000.c
+++ b/arch/mips/alchemy/common/gpiolib-au1000.c
@@ -36,7 +36,6 @@
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-au1x00/gpio.h>
 
-#if !defined(CONFIG_SOC_AU1000)
 static int gpio2_get(struct gpio_chip *chip, unsigned offset)
 {
        return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
@@ -63,7 +62,7 @@ static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
 {
        return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
 }
-#endif /* !defined(CONFIG_SOC_AU1000) */
+
 
 static int gpio1_get(struct gpio_chip *chip, unsigned offset)
 {
@@ -104,7 +103,6 @@ struct gpio_chip alchemy_gpio_chip[] = {
                .base                   = ALCHEMY_GPIO1_BASE,
                .ngpio                  = ALCHEMY_GPIO1_NUM,
        },
-#if !defined(CONFIG_SOC_AU1000)
        [1] = {
                .label                  = "alchemy-gpio2",
                .direction_input        = gpio2_direction_input,
@@ -115,15 +113,13 @@ struct gpio_chip alchemy_gpio_chip[] = {
                .base                   = ALCHEMY_GPIO2_BASE,
                .ngpio                  = ALCHEMY_GPIO2_NUM,
        },
-#endif
 };
 
 static int __init alchemy_gpiolib_init(void)
 {
        gpiochip_add(&alchemy_gpio_chip[0]);
-#if !defined(CONFIG_SOC_AU1000)
-       gpiochip_add(&alchemy_gpio_chip[1]);
-#endif
+       if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000)
+               gpiochip_add(&alchemy_gpio_chip[1]);
 
        return 0;
 }

diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index 9cf32d9dbb21a9dff5379a791823170152c029e2..62d2f136d94115d1334ff726881b77fd6a6ae4fa 100644 (file)
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -236,19 +236,19 @@ static inline int alchemy_gpio1_is_valid(int gpio)
 
 static inline int alchemy_gpio1_to_irq(int gpio)
 {
-#if defined(CONFIG_SOC_AU1000)
-       return au1000_gpio1_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1100)
-       return au1100_gpio1_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1500)
-       return au1500_gpio1_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1550)
-       return au1550_gpio1_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1200)
-       return au1200_gpio1_to_irq(gpio);
-#else
+       switch (alchemy_get_cputype()) {
+       case ALCHEMY_CPU_AU1000:
+               return au1000_gpio1_to_irq(gpio);
+       case ALCHEMY_CPU_AU1100:
+               return au1100_gpio1_to_irq(gpio);
+       case ALCHEMY_CPU_AU1500:
+               return au1500_gpio1_to_irq(gpio);
+       case ALCHEMY_CPU_AU1550:
+               return au1550_gpio1_to_irq(gpio);
+       case ALCHEMY_CPU_AU1200:
+               return au1200_gpio1_to_irq(gpio);
+       }
        return -ENXIO;
-#endif
 }
 
 /*
@@ -306,19 +306,19 @@ static inline int alchemy_gpio2_is_valid(int gpio)
 
 static inline int alchemy_gpio2_to_irq(int gpio)
 {
-#if defined(CONFIG_SOC_AU1000)
-       return au1000_gpio2_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1100)
-       return au1100_gpio2_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1500)
-       return au1500_gpio2_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1550)
-       return au1550_gpio2_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1200)
-       return au1200_gpio2_to_irq(gpio);
-#else
+       switch (alchemy_get_cputype()) {
+       case ALCHEMY_CPU_AU1000:
+               return au1000_gpio2_to_irq(gpio);
+       case ALCHEMY_CPU_AU1100:
+               return au1100_gpio2_to_irq(gpio);
+       case ALCHEMY_CPU_AU1500:
+               return au1500_gpio2_to_irq(gpio);
+       case ALCHEMY_CPU_AU1550:
+               return au1550_gpio2_to_irq(gpio);
+       case ALCHEMY_CPU_AU1200:
+               return au1200_gpio2_to_irq(gpio);
+       }
        return -ENXIO;
-#endif
 }
 
 /**********************************************************************/
@@ -374,10 +374,13 @@ static inline void alchemy_gpio2_enable_int(int gpio2)
 
        gpio2 -= ALCHEMY_GPIO2_BASE;
 
-#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
        /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
-       gpio2 -= 8;
-#endif
+       switch (alchemy_get_cputype()) {
+       case ALCHEMY_CPU_AU1100:
+       case ALCHEMY_CPU_AU1500:
+               gpio2 -= 8;
+       }
+
        local_irq_save(flags);
        __alchemy_gpio2_mod_int(gpio2, 1);
        local_irq_restore(flags);
@@ -395,10 +398,13 @@ static inline void alchemy_gpio2_disable_int(int gpio2)
 
        gpio2 -= ALCHEMY_GPIO2_BASE;
 
-#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
        /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
-       gpio2 -= 8;
-#endif
+       switch (alchemy_get_cputype()) {
+       case ALCHEMY_CPU_AU1100:
+       case ALCHEMY_CPU_AU1500:
+               gpio2 -= 8;
+       }
+
        local_irq_save(flags);
        __alchemy_gpio2_mod_int(gpio2, 0);
        local_irq_restore(flags);
@@ -484,19 +490,19 @@ static inline int alchemy_gpio_to_irq(int gpio)
 
 static inline int alchemy_irq_to_gpio(int irq)
 {
-#if defined(CONFIG_SOC_AU1000)
-       return au1000_irq_to_gpio(irq);
-#elif defined(CONFIG_SOC_AU1100)
-       return au1100_irq_to_gpio(irq);
-#elif defined(CONFIG_SOC_AU1500)
-       return au1500_irq_to_gpio(irq);
-#elif defined(CONFIG_SOC_AU1550)
-       return au1550_irq_to_gpio(irq);
-#elif defined(CONFIG_SOC_AU1200)
-       return au1200_irq_to_gpio(irq);
-#else
+       switch (alchemy_get_cputype()) {
+       case ALCHEMY_CPU_AU1000:
+               return au1000_irq_to_gpio(irq);
+       case ALCHEMY_CPU_AU1100:
+               return au1100_irq_to_gpio(irq);
+       case ALCHEMY_CPU_AU1500:
+               return au1500_irq_to_gpio(irq);
+       case ALCHEMY_CPU_AU1550:
+               return au1550_irq_to_gpio(irq);
+       case ALCHEMY_CPU_AU1200:
+               return au1200_irq_to_gpio(irq);
+       }
        return -ENXIO;
-#endif
 }
 
 /**********************************************************************/