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[COMMON] pinctrl: samsung: Fix 9610 pin bank struct
authorJaehyoung Choi <jkkkkk.choi@samsung.com>
Tue, 8 May 2018 05:41:58 +0000 (14:41 +0900)
committerJaehyoung Choi <jkkkkk.choi@samsung.com>
Wed, 9 May 2018 11:27:51 +0000 (20:27 +0900)
Change-Id: I21e54a3018482988ebd9c9c8c3f15e3ebc32cc2b
Signed-off-by: Jaehyoung Choi <jkkkkk.choi@samsung.com>
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c patch | blob | blame | history
drivers/pinctrl/samsung/pinctrl-exynos.h patch | blob | blame | history

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index bbf05ca68e28912968ab40c58316547c6e921a85..87b7adf3b49b1669f945898ba7e8d582b6f3663b 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -429,75 +429,77 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = {
 /* pin banks of exynos9610 pin-controller 0 (ALIVE) */
 static struct samsung_pin_bank_data exynos9610_pin_banks0[] = {
        EXYNOS8_PIN_BANK_EINTN(bank_type_7, 6, 0x000, "etc1"),
-       EXYNOS8_PIN_BANK_EINTW(bank_type_7, 8, 0x020, "gpa0", 0x00),
-       EXYNOS8_PIN_BANK_EINTW(bank_type_7, 8, 0x040, "gpa1", 0x04),
-       EXYNOS8_PIN_BANK_EINTW(bank_type_7, 8, 0x060, "gpa2", 0x08),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x020, "gpa0", 0x00, 0x00),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x040, "gpa1", 0x04, 0x08),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 8, 0x060, "gpa2", 0x08, 0x10),
        EXYNOS8_PIN_BANK_EINTW(bank_type_7, 8, 0x080, "gpq0", 0x0c),
 };
 
 /* pin banks of exynos9610 pin-controller 1 (CMGP) */
 static struct samsung_pin_bank_data exynos9610_pin_banks1[] = {
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x000, "gpm0", 0x00),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x020, "gpm1", 0x04),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x040, "gpm2", 0x08),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x060, "gpm3", 0x0C),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x080, "gpm4", 0x10),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x0A0, "gpm5", 0x14),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x0C0, "gpm6", 0x18),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x0E0, "gpm7", 0x1C),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x100, "gpm8", 0x20),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x120, "gpm9", 0x24),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x140, "gpm10", 0x28),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x160, "gpm11", 0x2C),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x180, "gpm12", 0x30),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x1A0, "gpm13", 0x34),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x1C0, "gpm14", 0x38),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x1E0, "gpm15", 0x3C),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x200, "gpm16", 0x40),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x220, "gpm17", 0x44),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x240, "gpm18", 0x48),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x260, "gpm19", 0x4C),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x280, "gpm20", 0x50),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x2A0, "gpm21", 0x54),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x2C0, "gpm22", 0x58),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x2E0, "gpm23", 0x5C),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x300, "gpm24", 0x60),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_7, 1, 0x320, "gpm25", 0x64),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x000, "gpm0", 0x00, 0x00),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x020, "gpm1", 0x04, 0x04),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x040, "gpm2", 0x08, 0x08),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x060, "gpm3", 0x0C, 0x0C),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x080, "gpm4", 0x10, 0x10),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x0A0, "gpm5", 0x14, 0x14),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x0C0, "gpm6", 0x18, 0x18),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x0E0, "gpm7", 0x1C, 0x1C),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x100, "gpm8", 0x20, 0x20),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x120, "gpm9", 0x24, 0x24),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x140, "gpm10", 0x28, 0x28),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x160, "gpm11", 0x2C, 0x2C),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x180, "gpm12", 0x30, 0x30),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x1A0, "gpm13", 0x34, 0x34),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x1C0, "gpm14", 0x38, 0x38),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x1E0, "gpm15", 0x3C, 0x3C),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x200, "gpm16", 0x40, 0x40),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x220, "gpm17", 0x44, 0x44),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x240, "gpm18", 0x48, 0x48),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x260, "gpm19", 0x4C, 0x4C),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x280, "gpm20", 0x50, 0x50),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x2A0, "gpm21", 0x54, 0x54),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x2C0, "gpm22", 0x58, 0x58),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x2E0, "gpm23", 0x5C, 0x5C),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x300, "gpm24", 0x60, 0x60),
+       EXYNOS9_PIN_BANK_EINTW(bank_type_7, 1, 0x320, "gpm25", 0x64, 0x64),
 };
 
+
 /* pin banks of exynos9610 pin-controller 2 (DISPAUD) */
 static struct samsung_pin_bank_data exynos9610_pin_banks2[] = {
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 5, 0x000, "gpb0", 0x00),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 4, 0x020, "gpb1", 0x04),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 5, 0x040, "gpb2", 0x08),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x000, "gpb0", 0x00, 0x00),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x020, "gpb1", 0x04, 0x08),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x040, "gpb2", 0x08, 0x0C),
 };
 
 /* pin banks of exynos9610 pin-controller 3 (FSYS) */
 static struct samsung_pin_bank_data exynos9610_pin_banks3[] = {
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 4, 0x000, "gpf0", 0x00),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x020, "gpf1", 0x04),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 6, 0x040, "gpf2", 0x08),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x000, "gpf0", 0x00, 0x00),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x020, "gpf1", 0x04, 0x04),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x040, "gpf2", 0x08, 0x0C),
 };
 
 /* pin banks of exynos9610 pin-controller 4 (TOP) */
 static struct samsung_pin_bank_data exynos9610_pin_banks4[] = {
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x000, "gpp0", 0x00),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 6, 0x020, "gpp1", 0x04),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x040, "gpp2", 0x08),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x060, "gpc0", 0x0C),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x080, "gpc1", 0x10),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 5, 0x0A0, "gpc2", 0x14),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x0C0, "gpg0", 0x18),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x0E0, "gpg1", 0x1C),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 8, 0x100, "gpg2", 0x20),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 6, 0x120, "gpg3", 0x24),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 3, 0x140, "gpg4", 0x28),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x000, "gpp0", 0x00, 0x00),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x020, "gpp1", 0x04, 0x08),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x040, "gpp2", 0x08, 0x10),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x060, "gpc0", 0x0C, 0x18),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x080, "gpc1", 0x10, 0x20),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x0A0, "gpc2", 0x14, 0x28),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x0C0, "gpg0", 0x18, 0x30),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x0E0, "gpg1", 0x1C, 0x38),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x100, "gpg2", 0x20, 0x40),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x120, "gpg3", 0x24, 0x48),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 3, 0x140, "gpg4", 0x28, 0x50),
 };
 
+
 /* pin banks of exynos9610 pin-controller 5 (SHUB) */
 static struct samsung_pin_bank_data exynos9610_pin_banks5[] = {
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 4, 0x000, "gph0", 0x00),
-       EXYNOS8_PIN_BANK_EINTG(bank_type_6, 3, 0x020, "gph1", 0x04),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x000, "gph0", 0x00, 0x00),
+       EXYNOS9_PIN_BANK_EINTG(bank_type_6, 3, 0x020, "gph1", 0x04, 0x04),
 };
 
 const struct samsung_pin_ctrl exynos9610_pin_ctrl[] = {
@@ -510,35 +512,35 @@ const struct samsung_pin_ctrl exynos9610_pin_ctrl[] = {
                .suspend        = exynos_pinctrl_suspend,
                .resume         = exynos_pinctrl_resume,
        }, {
-               /* pin-controller instance 1 AUD data */
+               /* pin-controller instance 1 CMGP data */
                .pin_banks      = exynos9610_pin_banks1,
                .nr_banks       = ARRAY_SIZE(exynos9610_pin_banks1),
-               //.eint_gpio_init = exynos_eint_gpio_init,
+               .eint_gpio_init = exynos_eint_gpio_init,
                .suspend        = exynos_pinctrl_suspend,
                .resume         = exynos_pinctrl_resume,
        }, {
-               /* pin-controller instance 2 CHUB data */
+               /* pin-controller instance 2 DISPAUD data */
                .pin_banks      = exynos9610_pin_banks2,
                .nr_banks       = ARRAY_SIZE(exynos9610_pin_banks2),
                .eint_gpio_init = exynos_eint_gpio_init,
                .suspend        = exynos_pinctrl_suspend,
                .resume         = exynos_pinctrl_resume,
        }, {
-               /* pin-controller instance 3 CMGP data */
+               /* pin-controller instance 3 FSYS data */
                .pin_banks      = exynos9610_pin_banks3,
                .nr_banks       = ARRAY_SIZE(exynos9610_pin_banks3),
                .eint_gpio_init = exynos_eint_gpio_init,
                .suspend        = exynos_pinctrl_suspend,
                .resume         = exynos_pinctrl_resume,
        }, {
-               /* pin-controller instance 4 FSYS0 data */
+               /* pin-controller instance 4 TOP data */
                .pin_banks      = exynos9610_pin_banks4,
                .nr_banks       = ARRAY_SIZE(exynos9610_pin_banks4),
                .eint_gpio_init = exynos_eint_gpio_init,
                .suspend        = exynos_pinctrl_suspend,
                .resume         = exynos_pinctrl_resume,
        }, {
-               /* pin-controller instance 5 FSYS1 data */
+               /* pin-controller instance 5 SHUB data */
                .pin_banks      = exynos9610_pin_banks5,
                .nr_banks       = ARRAY_SIZE(exynos9610_pin_banks5),
                .eint_gpio_init = exynos_eint_gpio_init,
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 0c8f052790fbfd40fff0cd4738b6c24d87590af1..38b1ad5da9e667c5c1857f5a41b934b0072936db 100644 (file)
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -148,6 +148,59 @@
                .name           = id                    \
        }
 
+#define EXYNOS9_PIN_BANK_EINTN(types, pins, reg, id)   \
+       {                                               \
+               .type           = &types,               \
+               .pctl_offset    = reg,                  \
+               .nr_pins        = pins,                 \
+               .eint_type      = EINT_TYPE_NONE,       \
+               .name           = id                    \
+       }
+
+#define EXYNOS9_PIN_BANK_EINTG(types, pins, reg, id, offs, fltcon_offs)        \
+       {                                               \
+               .type           = &types,               \
+               .pctl_offset    = reg,                  \
+               .nr_pins        = pins,                 \
+               .eint_type      = EINT_TYPE_GPIO,       \
+               .eint_offset    = offs,                 \
+               .fltcon_offset  = fltcon_offs,          \
+               .name           = id                    \
+       }
+
+#define EXYNOS9_PIN_BANK_EINTW(types, pins, reg, id, offs, fltcon_offs)        \
+       {                                               \
+               .type           = &types,               \
+               .pctl_offset    = reg,                  \
+               .nr_pins        = pins,                 \
+               .eint_type      = EINT_TYPE_WKUP,       \
+               .eint_offset    = offs,                 \
+               .fltcon_offset  = fltcon_offs,          \
+               .name           = id                    \
+       }
+
+#define EXYNOS9_PIN_BANK_EINTG(types, pins, reg, id, offs, fltcon_offs)        \
+       {                                               \
+               .type           = &types,               \
+               .pctl_offset    = reg,                  \
+               .nr_pins        = pins,                 \
+               .eint_type      = EINT_TYPE_GPIO,       \
+               .eint_offset    = offs,                 \
+               .fltcon_offset  = fltcon_offs,          \
+               .name           = id                    \
+       }
+
+#define EXYNOS9_PIN_BANK_EINTW(types, pins, reg, id, offs, fltcon_offs)        \
+       {                                               \
+               .type           = &types,               \
+               .pctl_offset    = reg,                  \
+               .nr_pins        = pins,                 \
+               .eint_type      = EINT_TYPE_WKUP,       \
+               .eint_offset    = offs,                 \
+               .fltcon_offset  = fltcon_offs,          \
+               .name           = id                    \
+       }
+
 /**
  * struct exynos_weint_data: irq specific data for all the wakeup interrupts
  * generated by the external wakeup interrupt controller.