#ifndef __NVKM_LTC_H__
#define __NVKM_LTC_H__
#include <core/subdev.h>
-struct nvkm_mm_node;
+#include <core/mm.h>
#define NVKM_LTC_MAX_ZBC_CNT 16
struct nvkm_ltc {
+ const struct nvkm_ltc_func *func;
struct nvkm_subdev subdev;
- int (*tags_alloc)(struct nvkm_ltc *, u32 count,
- struct nvkm_mm_node **);
- void (*tags_free)(struct nvkm_ltc *, struct nvkm_mm_node **);
- void (*tags_clear)(struct nvkm_ltc *, u32 first, u32 count);
+ u32 ltc_nr;
+ u32 lts_nr;
+
+ u32 num_tags;
+ u32 tag_base;
+ struct nvkm_mm tags;
+ struct nvkm_mm_node *tag_ram;
int zbc_min;
int zbc_max;
- int (*zbc_color_get)(struct nvkm_ltc *, int index, const u32[4]);
- int (*zbc_depth_get)(struct nvkm_ltc *, int index, const u32);
+ u32 zbc_color[NVKM_LTC_MAX_ZBC_CNT][4];
+ u32 zbc_depth[NVKM_LTC_MAX_ZBC_CNT];
};
-static inline struct nvkm_ltc *
-nvkm_ltc(void *obj)
-{
- return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_LTC);
-}
+int nvkm_ltc_tags_alloc(struct nvkm_ltc *, u32 count, struct nvkm_mm_node **);
+void nvkm_ltc_tags_free(struct nvkm_ltc *, struct nvkm_mm_node **);
+void nvkm_ltc_tags_clear(struct nvkm_ltc *, u32 first, u32 count);
+
+int nvkm_ltc_zbc_color_get(struct nvkm_ltc *, int index, const u32[4]);
+int nvkm_ltc_zbc_depth_get(struct nvkm_ltc *, int index, const u32);
-extern struct nvkm_oclass *gf100_ltc_oclass;
-extern struct nvkm_oclass *gk104_ltc_oclass;
-extern struct nvkm_oclass *gm107_ltc_oclass;
+int gf100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
+int gk104_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
+int gm107_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **);
#endif
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gf100_ltc_new,
+ .ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gf100_ltc_new,
+ .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gf100_ltc_new,
+ .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gf100_ltc_new,
+ .ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gf100_ltc_new,
+ .ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gf100_ltc_new,
+ .ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gf100_ltc_new,
+ .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = gf117_i2c_new,
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gf100_ltc_new,
+ .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = gf119_i2c_new,
.ibus = gf100_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gf100_ltc_new,
+ .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = gk104_i2c_new,
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gk104_ltc_new,
+ .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = gk104_i2c_new,
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gk104_ltc_new,
+ .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = gk104_i2c_new,
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gk104_ltc_new,
+ .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.fuse = gf100_fuse_new,
.ibus = gk20a_ibus_new,
.imem = gk20a_instmem_new,
-// .ltc = gk104_ltc_new,
+ .ltc = gk104_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .pmu = gk20a_pmu_new,
.i2c = gk104_i2c_new,
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gk104_ltc_new,
+ .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = gf119_i2c_new,
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gk104_ltc_new,
+ .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = gk104_i2c_new,
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gk104_ltc_new,
+ .ltc = gk104_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = gk104_i2c_new,
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gk104_ltc_new,
+ .ltc = gk104_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = gf119_i2c_new,
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gm107_ltc_new,
+ .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = gm204_i2c_new,
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gm107_ltc_new,
+ .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.i2c = gm204_i2c_new,
.ibus = gk104_ibus_new,
.imem = nv50_instmem_new,
-// .ltc = gm107_ltc_new,
+ .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
.fuse = gm107_fuse_new,
.ibus = gk20a_ibus_new,
.imem = gk20a_instmem_new,
-// .ltc = gm107_ltc_new,
+ .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mmu = gf100_mmu_new,
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
case 0xea:
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
- device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass;
gf100_gr_zbc_color_get(struct gf100_gr *gr, int format,
const u32 ds[4], const u32 l2[4])
{
- struct nvkm_ltc *ltc = nvkm_ltc(gr);
+ struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds));
memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2));
gr->zbc_color[zbc].format = format;
- ltc->zbc_color_get(ltc, zbc, l2);
+ nvkm_ltc_zbc_color_get(ltc, zbc, l2);
gf100_gr_zbc_clear_color(gr, zbc);
return zbc;
}
gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
const u32 ds, const u32 l2)
{
- struct nvkm_ltc *ltc = nvkm_ltc(gr);
+ struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
gr->zbc_depth[zbc].format = format;
gr->zbc_depth[zbc].ds = ds;
gr->zbc_depth[zbc].l2 = l2;
- ltc->zbc_depth_get(ltc, zbc, l2);
+ nvkm_ltc_zbc_depth_get(ltc, zbc, l2);
gf100_gr_zbc_clear_depth(gr, zbc);
return zbc;
}
0x00000000, 0x00000000, 0x00000000, 0x00000000 };
const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
- struct nvkm_ltc *ltc = nvkm_ltc(gr);
+ struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
int index;
if (!gr->zbc_color[0].format) {
mutex_lock(&ram->fb->subdev.mutex);
if (mem->tag)
- ltc->tags_free(ltc, &mem->tag);
+ nvkm_ltc_tags_free(ltc, &mem->tag);
__nv50_ram_put(ram, mem);
mutex_unlock(&ram->fb->subdev.mutex);
/* compression only works with lpages */
if (align == (1 << (17 - NVKM_RAM_MM_SHIFT))) {
int n = size >> 5;
- ltc->tags_alloc(ltc, n, &mem->tag);
+ nvkm_ltc_tags_alloc(ltc, n, &mem->tag);
}
if (unlikely(!mem->tag))
*/
#include "priv.h"
-static int
-nvkm_ltc_tags_alloc(struct nvkm_ltc *obj, u32 n, struct nvkm_mm_node **pnode)
-{
- struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
- int ret;
+#include <subdev/fb.h>
- ret = nvkm_mm_head(<c->tags, 0, 1, n, n, 1, pnode);
+int
+nvkm_ltc_tags_alloc(struct nvkm_ltc *ltc, u32 n, struct nvkm_mm_node **pnode)
+{
+ int ret = nvkm_mm_head(<c->tags, 0, 1, n, n, 1, pnode);
if (ret)
*pnode = NULL;
-
return ret;
}
-static void
-nvkm_ltc_tags_free(struct nvkm_ltc *obj, struct nvkm_mm_node **pnode)
+void
+nvkm_ltc_tags_free(struct nvkm_ltc *ltc, struct nvkm_mm_node **pnode)
{
- struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
nvkm_mm_free(<c->tags, pnode);
}
-static void
-nvkm_ltc_tags_clear(struct nvkm_ltc *obj, u32 first, u32 count)
+void
+nvkm_ltc_tags_clear(struct nvkm_ltc *ltc, u32 first, u32 count)
{
- struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
- const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
const u32 limit = first + count - 1;
BUG_ON((first > limit) || (limit >= ltc->num_tags));
- impl->cbc_clear(ltc, first, limit);
- impl->cbc_wait(ltc);
+ ltc->func->cbc_clear(ltc, first, limit);
+ ltc->func->cbc_wait(ltc);
}
-static int
-nvkm_ltc_zbc_color_get(struct nvkm_ltc *obj, int index, const u32 color[4])
+int
+nvkm_ltc_zbc_color_get(struct nvkm_ltc *ltc, int index, const u32 color[4])
{
- struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
- const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
memcpy(ltc->zbc_color[index], color, sizeof(ltc->zbc_color[index]));
- impl->zbc_clear_color(ltc, index, color);
+ ltc->func->zbc_clear_color(ltc, index, color);
return index;
}
-static int
-nvkm_ltc_zbc_depth_get(struct nvkm_ltc *obj, int index, const u32 depth)
+int
+nvkm_ltc_zbc_depth_get(struct nvkm_ltc *ltc, int index, const u32 depth)
{
- struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base);
- const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
ltc->zbc_depth[index] = depth;
- impl->zbc_clear_depth(ltc, index, depth);
+ ltc->func->zbc_clear_depth(ltc, index, depth);
return index;
}
-int
-_nvkm_ltc_init(struct nvkm_object *object)
+static void
+nvkm_ltc_intr(struct nvkm_subdev *subdev)
{
- struct nvkm_ltc_priv *ltc = (void *)object;
- const struct nvkm_ltc_impl *impl = (void *)nv_oclass(object);
- int ret, i;
+ struct nvkm_ltc *ltc = nvkm_ltc(subdev);
+ ltc->func->intr(ltc);
+}
- ret = nvkm_subdev_init_old(<c->base.subdev);
- if (ret)
- return ret;
+static int
+nvkm_ltc_oneinit(struct nvkm_subdev *subdev)
+{
+ struct nvkm_ltc *ltc = nvkm_ltc(subdev);
+ return ltc->func->oneinit(ltc);
+}
+
+static int
+nvkm_ltc_init(struct nvkm_subdev *subdev)
+{
+ struct nvkm_ltc *ltc = nvkm_ltc(subdev);
+ int i;
- for (i = ltc->base.zbc_min; i <= ltc->base.zbc_max; i++) {
- impl->zbc_clear_color(ltc, i, ltc->zbc_color[i]);
- impl->zbc_clear_depth(ltc, i, ltc->zbc_depth[i]);
+ for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
+ ltc->func->zbc_clear_color(ltc, i, ltc->zbc_color[i]);
+ ltc->func->zbc_clear_depth(ltc, i, ltc->zbc_depth[i]);
}
+ ltc->func->init(ltc);
return 0;
}
+static void *
+nvkm_ltc_dtor(struct nvkm_subdev *subdev)
+{
+ struct nvkm_ltc *ltc = nvkm_ltc(subdev);
+ struct nvkm_ram *ram = ltc->subdev.device->fb->ram;
+ nvkm_mm_fini(<c->tags);
+ if (ram)
+ nvkm_mm_free(&ram->vram, <c->tag_ram);
+ return ltc;
+}
+
+static const struct nvkm_subdev_func
+nvkm_ltc = {
+ .dtor = nvkm_ltc_dtor,
+ .oneinit = nvkm_ltc_oneinit,
+ .init = nvkm_ltc_init,
+ .intr = nvkm_ltc_intr,
+};
+
int
-nvkm_ltc_create_(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, int length, void **pobject)
+nvkm_ltc_new_(const struct nvkm_ltc_func *func, struct nvkm_device *device,
+ int index, struct nvkm_ltc **pltc)
{
- const struct nvkm_ltc_impl *impl = (void *)oclass;
- struct nvkm_ltc_priv *ltc;
- int ret;
+ struct nvkm_ltc *ltc;
- ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PLTCG",
- "l2c", length, pobject);
- ltc = *pobject;
- if (ret)
- return ret;
-
- memset(ltc->zbc_color, 0x00, sizeof(ltc->zbc_color));
- memset(ltc->zbc_depth, 0x00, sizeof(ltc->zbc_depth));
-
- ltc->base.subdev.intr = impl->intr;
- ltc->base.tags_alloc = nvkm_ltc_tags_alloc;
- ltc->base.tags_free = nvkm_ltc_tags_free;
- ltc->base.tags_clear = nvkm_ltc_tags_clear;
- ltc->base.zbc_min = 1; /* reserve 0 for disabled */
- ltc->base.zbc_max = min(impl->zbc, NVKM_LTC_MAX_ZBC_CNT) - 1;
- ltc->base.zbc_color_get = nvkm_ltc_zbc_color_get;
- ltc->base.zbc_depth_get = nvkm_ltc_zbc_depth_get;
+ if (!(ltc = *pltc = kzalloc(sizeof(*ltc), GFP_KERNEL)))
+ return -ENOMEM;
+
+ nvkm_subdev_ctor(&nvkm_ltc, device, index, 0, <c->subdev);
+ ltc->func = func;
+ ltc->zbc_min = 1; /* reserve 0 for disabled */
+ ltc->zbc_max = min(func->zbc, NVKM_LTC_MAX_ZBC_CNT) - 1;
return 0;
}
#include <subdev/timer.h>
void
-gf100_ltc_cbc_clear(struct nvkm_ltc_priv *ltc, u32 start, u32 limit)
+gf100_ltc_cbc_clear(struct nvkm_ltc *ltc, u32 start, u32 limit)
{
- struct nvkm_device *device = ltc->base.subdev.device;
+ struct nvkm_device *device = ltc->subdev.device;
nvkm_wr32(device, 0x17e8cc, start);
nvkm_wr32(device, 0x17e8d0, limit);
nvkm_wr32(device, 0x17e8c8, 0x00000004);
}
void
-gf100_ltc_cbc_wait(struct nvkm_ltc_priv *ltc)
+gf100_ltc_cbc_wait(struct nvkm_ltc *ltc)
{
- struct nvkm_device *device = ltc->base.subdev.device;
+ struct nvkm_device *device = ltc->subdev.device;
int c, s;
for (c = 0; c < ltc->ltc_nr; c++) {
for (s = 0; s < ltc->lts_nr; s++) {
}
void
-gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4])
+gf100_ltc_zbc_clear_color(struct nvkm_ltc *ltc, int i, const u32 color[4])
{
- struct nvkm_device *device = ltc->base.subdev.device;
+ struct nvkm_device *device = ltc->subdev.device;
nvkm_mask(device, 0x17ea44, 0x0000000f, i);
nvkm_wr32(device, 0x17ea48, color[0]);
nvkm_wr32(device, 0x17ea4c, color[1]);
}
void
-gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *ltc, int i, const u32 depth)
+gf100_ltc_zbc_clear_depth(struct nvkm_ltc *ltc, int i, const u32 depth)
{
- struct nvkm_device *device = ltc->base.subdev.device;
+ struct nvkm_device *device = ltc->subdev.device;
nvkm_mask(device, 0x17ea44, 0x0000000f, i);
nvkm_wr32(device, 0x17ea58, depth);
}
};
static void
-gf100_ltc_lts_intr(struct nvkm_ltc_priv *ltc, int c, int s)
+gf100_ltc_lts_intr(struct nvkm_ltc *ltc, int c, int s)
{
- struct nvkm_subdev *subdev = <c->base.subdev;
+ struct nvkm_subdev *subdev = <c->subdev;
struct nvkm_device *device = subdev->device;
u32 base = 0x141000 + (c * 0x2000) + (s * 0x400);
u32 intr = nvkm_rd32(device, base + 0x020);
}
void
-gf100_ltc_intr(struct nvkm_subdev *subdev)
+gf100_ltc_intr(struct nvkm_ltc *ltc)
{
- struct nvkm_ltc_priv *ltc = (void *)subdev;
- struct nvkm_device *device = ltc->base.subdev.device;
+ struct nvkm_device *device = ltc->subdev.device;
u32 mask;
mask = nvkm_rd32(device, 0x00017c);
}
}
-static int
-gf100_ltc_init(struct nvkm_object *object)
-{
- struct nvkm_ltc_priv *ltc = (void *)object;
- struct nvkm_device *device = ltc->base.subdev.device;
- u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);
- int ret;
-
- ret = nvkm_ltc_init(ltc);
- if (ret)
- return ret;
-
- nvkm_mask(device, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
- nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr);
- nvkm_wr32(device, 0x17e8d4, ltc->tag_base);
- nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
- return 0;
-}
-
-void
-gf100_ltc_dtor(struct nvkm_object *object)
-{
- struct nvkm_ltc_priv *ltc = (void *)object;
- struct nvkm_ram *ram = ltc->base.subdev.device->fb->ram;
-
- nvkm_mm_fini(<c->tags);
- if (ram)
- nvkm_mm_free(&ram->vram, <c->tag_ram);
-
- nvkm_ltc_destroy(ltc);
-}
-
/* TODO: Figure out tag memory details and drop the over-cautious allocation.
*/
int
-gf100_ltc_init_tag_ram(struct nvkm_ltc_priv *ltc)
+gf100_ltc_oneinit_tag_ram(struct nvkm_ltc *ltc)
{
- struct nvkm_ram *ram = ltc->base.subdev.device->fb->ram;
+ struct nvkm_ram *ram = ltc->subdev.device->fb->ram;
u32 tag_size, tag_margin, tag_align;
int ret;
}
mm_init:
- ret = nvkm_mm_init(<c->tags, 0, ltc->num_tags, 1);
- return ret;
+ return nvkm_mm_init(<c->tags, 0, ltc->num_tags, 1);
}
int
-gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+gf100_ltc_oneinit(struct nvkm_ltc *ltc)
{
- struct nvkm_device *device = (void *)parent;
- struct nvkm_ltc_priv *ltc;
- u32 parts, mask;
- int ret, i;
-
- ret = nvkm_ltc_create(parent, engine, oclass, <c);
- *pobject = nv_object(ltc);
- if (ret)
- return ret;
+ struct nvkm_device *device = ltc->subdev.device;
+ const u32 parts = nvkm_rd32(device, 0x022438);
+ const u32 mask = nvkm_rd32(device, 0x022554);
+ const u32 slice = nvkm_rd32(device, 0x17e8dc) >> 28;
+ int i;
- parts = nvkm_rd32(device, 0x022438);
- mask = nvkm_rd32(device, 0x022554);
for (i = 0; i < parts; i++) {
if (!(mask & (1 << i)))
ltc->ltc_nr++;
}
- ltc->lts_nr = nvkm_rd32(device, 0x17e8dc) >> 28;
+ ltc->lts_nr = slice;
+
+ return gf100_ltc_oneinit_tag_ram(ltc);
+}
- ret = gf100_ltc_init_tag_ram(ltc);
- if (ret)
- return ret;
+static void
+gf100_ltc_init(struct nvkm_ltc *ltc)
+{
+ struct nvkm_device *device = ltc->subdev.device;
+ u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);
- nv_subdev(ltc)->intr = gf100_ltc_intr;
- return 0;
+ nvkm_mask(device, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
+ nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr);
+ nvkm_wr32(device, 0x17e8d4, ltc->tag_base);
+ nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
}
-struct nvkm_oclass *
-gf100_ltc_oclass = &(struct nvkm_ltc_impl) {
- .base.handle = NV_SUBDEV(LTC, 0xc0),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gf100_ltc_ctor,
- .dtor = gf100_ltc_dtor,
- .init = gf100_ltc_init,
- .fini = _nvkm_ltc_fini,
- },
+static const struct nvkm_ltc_func
+gf100_ltc = {
+ .oneinit = gf100_ltc_oneinit,
+ .init = gf100_ltc_init,
.intr = gf100_ltc_intr,
.cbc_clear = gf100_ltc_cbc_clear,
.cbc_wait = gf100_ltc_cbc_wait,
.zbc = 16,
.zbc_clear_color = gf100_ltc_zbc_clear_color,
.zbc_clear_depth = gf100_ltc_zbc_clear_depth,
-}.base;
+};
+
+int
+gf100_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc)
+{
+ return nvkm_ltc_new_(&gf100_ltc, device, index, pltc);
+}
*/
#include "priv.h"
-static int
-gk104_ltc_init(struct nvkm_object *object)
+static void
+gk104_ltc_init(struct nvkm_ltc *ltc)
{
- struct nvkm_ltc_priv *ltc = (void *)object;
- struct nvkm_device *device = ltc->base.subdev.device;
+ struct nvkm_device *device = ltc->subdev.device;
u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);
- int ret;
-
- ret = nvkm_ltc_init(ltc);
- if (ret)
- return ret;
nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr);
nvkm_wr32(device, 0x17e000, ltc->ltc_nr);
nvkm_wr32(device, 0x17e8d4, ltc->tag_base);
nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
- return 0;
}
-struct nvkm_oclass *
-gk104_ltc_oclass = &(struct nvkm_ltc_impl) {
- .base.handle = NV_SUBDEV(LTC, 0xe4),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gf100_ltc_ctor,
- .dtor = gf100_ltc_dtor,
- .init = gk104_ltc_init,
- .fini = _nvkm_ltc_fini,
- },
+static const struct nvkm_ltc_func
+gk104_ltc = {
+ .oneinit = gf100_ltc_oneinit,
+ .init = gk104_ltc_init,
.intr = gf100_ltc_intr,
.cbc_clear = gf100_ltc_cbc_clear,
.cbc_wait = gf100_ltc_cbc_wait,
.zbc = 16,
.zbc_clear_color = gf100_ltc_zbc_clear_color,
.zbc_clear_depth = gf100_ltc_zbc_clear_depth,
-}.base;
+};
+
+int
+gk104_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc)
+{
+ return nvkm_ltc_new_(&gk104_ltc, device, index, pltc);
+}
#include <subdev/timer.h>
static void
-gm107_ltc_cbc_clear(struct nvkm_ltc_priv *ltc, u32 start, u32 limit)
+gm107_ltc_cbc_clear(struct nvkm_ltc *ltc, u32 start, u32 limit)
{
- struct nvkm_device *device = ltc->base.subdev.device;
+ struct nvkm_device *device = ltc->subdev.device;
nvkm_wr32(device, 0x17e270, start);
nvkm_wr32(device, 0x17e274, limit);
nvkm_wr32(device, 0x17e26c, 0x00000004);
}
static void
-gm107_ltc_cbc_wait(struct nvkm_ltc_priv *ltc)
+gm107_ltc_cbc_wait(struct nvkm_ltc *ltc)
{
- struct nvkm_device *device = ltc->base.subdev.device;
+ struct nvkm_device *device = ltc->subdev.device;
int c, s;
for (c = 0; c < ltc->ltc_nr; c++) {
for (s = 0; s < ltc->lts_nr; s++) {
}
static void
-gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4])
+gm107_ltc_zbc_clear_color(struct nvkm_ltc *ltc, int i, const u32 color[4])
{
- struct nvkm_device *device = ltc->base.subdev.device;
+ struct nvkm_device *device = ltc->subdev.device;
nvkm_mask(device, 0x17e338, 0x0000000f, i);
nvkm_wr32(device, 0x17e33c, color[0]);
nvkm_wr32(device, 0x17e340, color[1]);
}
static void
-gm107_ltc_zbc_clear_depth(struct nvkm_ltc_priv *ltc, int i, const u32 depth)
+gm107_ltc_zbc_clear_depth(struct nvkm_ltc *ltc, int i, const u32 depth)
{
- struct nvkm_device *device = ltc->base.subdev.device;
+ struct nvkm_device *device = ltc->subdev.device;
nvkm_mask(device, 0x17e338, 0x0000000f, i);
nvkm_wr32(device, 0x17e34c, depth);
}
static void
-gm107_ltc_lts_isr(struct nvkm_ltc_priv *ltc, int c, int s)
+gm107_ltc_lts_isr(struct nvkm_ltc *ltc, int c, int s)
{
- struct nvkm_subdev *subdev = <c->base.subdev;
+ struct nvkm_subdev *subdev = <c->subdev;
struct nvkm_device *device = subdev->device;
u32 base = 0x140000 + (c * 0x2000) + (s * 0x400);
u32 stat = nvkm_rd32(device, base + 0x00c);
}
static void
-gm107_ltc_intr(struct nvkm_subdev *subdev)
+gm107_ltc_intr(struct nvkm_ltc *ltc)
{
- struct nvkm_ltc_priv *ltc = (void *)subdev;
- struct nvkm_device *device = ltc->base.subdev.device;
+ struct nvkm_device *device = ltc->subdev.device;
u32 mask;
mask = nvkm_rd32(device, 0x00017c);
}
static int
-gm107_ltc_init(struct nvkm_object *object)
+gm107_ltc_oneinit(struct nvkm_ltc *ltc)
{
- struct nvkm_ltc_priv *ltc = (void *)object;
- struct nvkm_device *device = ltc->base.subdev.device;
- u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);
- int ret;
-
- ret = nvkm_ltc_init(ltc);
- if (ret)
- return ret;
-
- nvkm_wr32(device, 0x17e27c, ltc->ltc_nr);
- nvkm_wr32(device, 0x17e278, ltc->tag_base);
- nvkm_mask(device, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
- return 0;
-}
+ struct nvkm_device *device = ltc->subdev.device;
+ const u32 parts = nvkm_rd32(device, 0x022438);
+ const u32 mask = nvkm_rd32(device, 0x021c14);
+ const u32 slice = nvkm_rd32(device, 0x17e280) >> 28;
+ int i;
-static int
-gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
-{
- struct nvkm_device *device = (void *)parent;
- struct nvkm_ltc_priv *ltc;
- u32 parts, mask;
- int ret, i;
-
- ret = nvkm_ltc_create(parent, engine, oclass, <c);
- *pobject = nv_object(ltc);
- if (ret)
- return ret;
-
- parts = nvkm_rd32(device, 0x022438);
- mask = nvkm_rd32(device, 0x021c14);
for (i = 0; i < parts; i++) {
if (!(mask & (1 << i)))
ltc->ltc_nr++;
}
- ltc->lts_nr = nvkm_rd32(device, 0x17e280) >> 28;
+ ltc->lts_nr = slice;
+
+ return gf100_ltc_oneinit_tag_ram(ltc);
+}
- ret = gf100_ltc_init_tag_ram(ltc);
- if (ret)
- return ret;
+static void
+gm107_ltc_init(struct nvkm_ltc *ltc)
+{
+ struct nvkm_device *device = ltc->subdev.device;
+ u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001);
- return 0;
+ nvkm_wr32(device, 0x17e27c, ltc->ltc_nr);
+ nvkm_wr32(device, 0x17e278, ltc->tag_base);
+ nvkm_mask(device, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
}
-struct nvkm_oclass *
-gm107_ltc_oclass = &(struct nvkm_ltc_impl) {
- .base.handle = NV_SUBDEV(LTC, 0xff),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gm107_ltc_ctor,
- .dtor = gf100_ltc_dtor,
- .init = gm107_ltc_init,
- .fini = _nvkm_ltc_fini,
- },
+static const struct nvkm_ltc_func
+gm107_ltc = {
+ .oneinit = gm107_ltc_oneinit,
+ .init = gm107_ltc_init,
.intr = gm107_ltc_intr,
.cbc_clear = gm107_ltc_cbc_clear,
.cbc_wait = gm107_ltc_cbc_wait,
.zbc = 16,
.zbc_clear_color = gm107_ltc_zbc_clear_color,
.zbc_clear_depth = gm107_ltc_zbc_clear_depth,
-}.base;
+};
+
+int
+gm107_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc)
+{
+ return nvkm_ltc_new_(&gm107_ltc, device, index, pltc);
+}
#ifndef __NVKM_LTC_PRIV_H__
#define __NVKM_LTC_PRIV_H__
+#define nvkm_ltc(p) container_of((p), struct nvkm_ltc, subdev)
#include <subdev/ltc.h>
-#include <core/mm.h>
-struct nvkm_fb;
+int nvkm_ltc_new_(const struct nvkm_ltc_func *, struct nvkm_device *,
+ int index, struct nvkm_ltc **);
-struct nvkm_ltc_priv {
- struct nvkm_ltc base;
- u32 ltc_nr;
- u32 lts_nr;
+struct nvkm_ltc_func {
+ int (*oneinit)(struct nvkm_ltc *);
+ void (*init)(struct nvkm_ltc *);
+ void (*intr)(struct nvkm_ltc *);
- u32 num_tags;
- u32 tag_base;
- struct nvkm_mm tags;
- struct nvkm_mm_node *tag_ram;
-
- u32 zbc_color[NVKM_LTC_MAX_ZBC_CNT][4];
- u32 zbc_depth[NVKM_LTC_MAX_ZBC_CNT];
-};
-
-#define nvkm_ltc_create(p,e,o,d) \
- nvkm_ltc_create_((p), (e), (o), sizeof(**d), (void **)d)
-#define nvkm_ltc_destroy(p) ({ \
- struct nvkm_ltc_priv *_priv = (p); \
- _nvkm_ltc_dtor(nv_object(_priv)); \
-})
-#define nvkm_ltc_init(p) ({ \
- struct nvkm_ltc_priv *_priv = (p); \
- _nvkm_ltc_init(nv_object(_priv)); \
-})
-#define nvkm_ltc_fini(p,s) ({ \
- struct nvkm_ltc_priv *_priv = (p); \
- _nvkm_ltc_fini(nv_object(_priv), (s)); \
-})
-
-int nvkm_ltc_create_(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, int, void **);
-
-#define _nvkm_ltc_dtor _nvkm_subdev_dtor
-int _nvkm_ltc_init(struct nvkm_object *);
-#define _nvkm_ltc_fini _nvkm_subdev_fini
-
-int gf100_ltc_ctor(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, void *, u32,
- struct nvkm_object **);
-void gf100_ltc_dtor(struct nvkm_object *);
-int gf100_ltc_init_tag_ram(struct nvkm_ltc_priv *);
-int gf100_ltc_tags_alloc(struct nvkm_ltc *, u32, struct nvkm_mm_node **);
-void gf100_ltc_tags_free(struct nvkm_ltc *, struct nvkm_mm_node **);
-
-struct nvkm_ltc_impl {
- struct nvkm_oclass base;
- void (*intr)(struct nvkm_subdev *);
-
- void (*cbc_clear)(struct nvkm_ltc_priv *, u32 start, u32 limit);
- void (*cbc_wait)(struct nvkm_ltc_priv *);
+ void (*cbc_clear)(struct nvkm_ltc *, u32 start, u32 limit);
+ void (*cbc_wait)(struct nvkm_ltc *);
int zbc;
- void (*zbc_clear_color)(struct nvkm_ltc_priv *, int, const u32[4]);
- void (*zbc_clear_depth)(struct nvkm_ltc_priv *, int, const u32);
+ void (*zbc_clear_color)(struct nvkm_ltc *, int, const u32[4]);
+ void (*zbc_clear_depth)(struct nvkm_ltc *, int, const u32);
};
-void gf100_ltc_intr(struct nvkm_subdev *);
-void gf100_ltc_cbc_clear(struct nvkm_ltc_priv *, u32, u32);
-void gf100_ltc_cbc_wait(struct nvkm_ltc_priv *);
-void gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *, int, const u32[4]);
-void gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *, int, const u32);
+int gf100_ltc_oneinit(struct nvkm_ltc *);
+int gf100_ltc_oneinit_tag_ram(struct nvkm_ltc *);
+void gf100_ltc_intr(struct nvkm_ltc *);
+void gf100_ltc_cbc_clear(struct nvkm_ltc *, u32, u32);
+void gf100_ltc_cbc_wait(struct nvkm_ltc *);
+void gf100_ltc_zbc_clear_color(struct nvkm_ltc *, int, const u32[4]);
+void gf100_ltc_zbc_clear_depth(struct nvkm_ltc *, int, const u32);
#endif
pte <<= 3;
if (mem->tag) {
- struct nvkm_ltc *ltc = nvkm_ltc(vma->vm->mmu);
+ struct nvkm_ltc *ltc = vma->vm->mmu->subdev.device->ltc;
u32 tag = mem->tag->offset + (delta >> 17);
phys |= (u64)tag << (32 + 12);
next |= (u64)1 << (32 + 12);
- ltc->tags_clear(ltc, tag, cnt);
+ nvkm_ltc_tags_clear(ltc, tag, cnt);
}
nvkm_kmap(pgt);
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / commitdiff