#include <core/event.h>
struct nvkm_disp {
- struct nvkm_engine engine;
const struct nvkm_disp_func *func;
+ struct nvkm_engine engine;
struct nvkm_oproxy *client;
struct nvkm_event hpd;
struct nvkm_event vblank;
-};
-struct nvkm_disp_func {
- const struct nvkm_disp_oclass *root;
+ struct {
+ int nr;
+ } head;
};
-extern struct nvkm_oclass *nv04_disp_oclass;
-extern struct nvkm_oclass *nv50_disp_oclass;
-extern struct nvkm_oclass *g84_disp_oclass;
-extern struct nvkm_oclass *gt200_disp_oclass;
-extern struct nvkm_oclass *g94_disp_oclass;
-extern struct nvkm_oclass *gt215_disp_oclass;
-extern struct nvkm_oclass *gf110_disp_oclass;
-extern struct nvkm_oclass *gk104_disp_oclass;
-extern struct nvkm_oclass *gk110_disp_oclass;
-extern struct nvkm_oclass *gm107_disp_oclass;
-extern struct nvkm_oclass *gm204_disp_oclass;
+int nv04_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
+int nv50_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
+int g84_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
+int gt200_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
+int g94_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
+int gt215_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
+int gf119_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
+int gk104_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
+int gk110_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
+int gm107_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
+int gm204_disp_new(struct nvkm_device *, int, struct nvkm_disp **);
#endif
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv04_fifo_new,
// .gr = nv04_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv04_fifo_new,
// .gr = nv04_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .gr = nv10_gr_new,
};
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv10_fifo_new,
// .gr = nv10_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv10_fifo_new,
// .gr = nv10_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv10_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv10_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv10_fifo_new,
// .gr = nv10_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv10_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv20_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv25_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv25_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv2a_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv30_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv30_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv34_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv35_gr_new,
.mc = nv04_mc_new,
.mmu = nv04_mmu_new,
.timer = nv04_timer_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv35_gr_new,
.therm = nv40_therm_new,
.timer = nv40_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv50_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv50_disp_new,
+ .disp = nv50_disp_new,
.dma = nv50_dma_new,
// .fifo = nv50_fifo_new,
// .gr = nv50_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.therm = nv40_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = nv04_disp_new,
+ .disp = nv04_disp_new,
.dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
.volt = nv40_volt_new,
.bsp = g84_bsp_new,
.cipher = g84_cipher_new,
-// .disp = g84_disp_new,
+ .disp = g84_disp_new,
.dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.volt = nv40_volt_new,
.bsp = g84_bsp_new,
.cipher = g84_cipher_new,
-// .disp = g84_disp_new,
+ .disp = g84_disp_new,
.dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.volt = nv40_volt_new,
.bsp = g84_bsp_new,
.cipher = g84_cipher_new,
-// .disp = g84_disp_new,
+ .disp = g84_disp_new,
.dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.volt = nv40_volt_new,
.bsp = g84_bsp_new,
.cipher = g84_cipher_new,
-// .disp = g94_disp_new,
+ .disp = g94_disp_new,
.dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.vp = g84_vp_new,
.cipher = g84_cipher_new,
.bsp = g84_bsp_new,
-// .disp = g94_disp_new,
+ .disp = g94_disp_new,
// .pm = g84_pm_new,
};
.sec = g98_sec_new,
.msvld = g98_msvld_new,
.msppp = g98_msppp_new,
-// .disp = g94_disp_new,
+ .disp = g94_disp_new,
// .pm = g84_pm_new,
};
.volt = nv40_volt_new,
.bsp = g84_bsp_new,
.cipher = g84_cipher_new,
-// .disp = gt200_disp_new,
+ .disp = gt200_disp_new,
.dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
.ce[0] = gt215_ce_new,
-// .disp = gt215_disp_new,
+ .disp = gt215_disp_new,
.dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
.ce[0] = gt215_ce_new,
-// .disp = gt215_disp_new,
+ .disp = gt215_disp_new,
.dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
.ce[0] = gt215_ce_new,
-// .disp = gt215_disp_new,
+ .disp = gt215_disp_new,
.dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = g94_disp_new,
+ .disp = g94_disp_new,
.dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
-// .disp = g94_disp_new,
+ .disp = g94_disp_new,
.dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
.ce[0] = gt215_ce_new,
-// .disp = gt215_disp_new,
+ .disp = gt215_disp_new,
.dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
.volt = nv40_volt_new,
.ce[0] = gf100_ce_new,
.ce[1] = gf100_ce_new,
-// .disp = gt215_disp_new,
+ .disp = gt215_disp_new,
.dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf100_gr_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
.ce[0] = gf100_ce_new,
-// .disp = gt215_disp_new,
+ .disp = gt215_disp_new,
.dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf108_gr_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
.ce[0] = gf100_ce_new,
-// .disp = gt215_disp_new,
+ .disp = gt215_disp_new,
.dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf104_gr_new,
.volt = nv40_volt_new,
.ce[0] = gf100_ce_new,
.ce[1] = gf100_ce_new,
-// .disp = gt215_disp_new,
+ .disp = gt215_disp_new,
.dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf104_gr_new,
.volt = nv40_volt_new,
.ce[0] = gf100_ce_new,
.ce[1] = gf100_ce_new,
-// .disp = gt215_disp_new,
+ .disp = gt215_disp_new,
.dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf110_gr_new,
.volt = nv40_volt_new,
.ce[0] = gf100_ce_new,
.ce[1] = gf100_ce_new,
-// .disp = gt215_disp_new,
+ .disp = gt215_disp_new,
.dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf104_gr_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
.ce[0] = gf100_ce_new,
-// .disp = gt215_disp_new,
+ .disp = gt215_disp_new,
.dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf104_gr_new,
.therm = gf119_therm_new,
.timer = nv41_timer_new,
.ce[0] = gf100_ce_new,
-// .disp = gf119_disp_new,
+ .disp = gf119_disp_new,
.dma = gf119_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf117_gr_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
.ce[0] = gf100_ce_new,
-// .disp = gf119_disp_new,
+ .disp = gf119_disp_new,
.dma = gf119_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf119_gr_new,
.ce[0] = gk104_ce_new,
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
-// .disp = gk104_disp_new,
+ .disp = gk104_disp_new,
.dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk104_gr_new,
.ce[0] = gk104_ce_new,
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
-// .disp = gk104_disp_new,
+ .disp = gk104_disp_new,
.dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk104_gr_new,
.ce[0] = gk104_ce_new,
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
-// .disp = gk104_disp_new,
+ .disp = gk104_disp_new,
.dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk104_gr_new,
.ce[0] = gk104_ce_new,
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
-// .disp = gk110_disp_new,
+ .disp = gk110_disp_new,
.dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk110_gr_new,
.ce[0] = gk104_ce_new,
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
-// .disp = gk110_disp_new,
+ .disp = gk110_disp_new,
.dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk110b_gr_new,
.ce[0] = gk104_ce_new,
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
-// .disp = gk110_disp_new,
+ .disp = gk110_disp_new,
.dma = gf119_dma_new,
// .fifo = gk208_fifo_new,
// .gr = gk208_gr_new,
.ce[0] = gk104_ce_new,
.ce[1] = gk104_ce_new,
.ce[2] = gk104_ce_new,
-// .disp = gk110_disp_new,
+ .disp = gk110_disp_new,
.dma = gf119_dma_new,
// .fifo = gk208_fifo_new,
// .gr = gk208_gr_new,
.timer = gk20a_timer_new,
.ce[0] = gk104_ce_new,
.ce[2] = gk104_ce_new,
-// .disp = gm107_disp_new,
+ .disp = gm107_disp_new,
.dma = gf119_dma_new,
// .fifo = gk208_fifo_new,
// .gr = gm107_gr_new,
.ce[0] = gm204_ce_new,
.ce[1] = gm204_ce_new,
.ce[2] = gm204_ce_new,
-// .disp = gm204_disp_new,
+ .disp = gm204_disp_new,
.dma = gf119_dma_new,
// .fifo = gm204_fifo_new,
// .gr = gm204_gr_new,
.ce[0] = gm204_ce_new,
.ce[1] = gm204_ce_new,
.ce[2] = gm204_ce_new,
-// .disp = gm204_disp_new,
+ .disp = gm204_disp_new,
.dma = gf119_dma_new,
// .fifo = gm204_fifo_new,
// .gr = gm206_gr_new,
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc4:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc3:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xce:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xcf:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc1:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
break;
case 0xc8:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xd9:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
break;
case 0xd7:
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
break;
default:
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe7:
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe6:
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xea:
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0xf1:
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0x106:
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
break;
case 0x108:
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
break;
default:
return -EINVAL;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
#if 0
#endif
#if 0
device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
#if 0
#endif
break;
device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gm204_disp_oclass;
#if 0
#endif
break;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x05:
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
default:
return -EINVAL;
switch (device->chipset) {
case 0x10:
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x15:
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x16:
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x1a:
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x11:
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x17:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x1f:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x18:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
default:
return -EINVAL;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x25:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x28:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x2a:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
default:
return -EINVAL;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x35:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x31:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x36:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x34:
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
default:
return -EINVAL;
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x41:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x42:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x43:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x45:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x47:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x49:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4b:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x44:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x46:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4a:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4c:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4e:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x63:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x67:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x68:
device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
default:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
break;
case 0x84:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x86:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x92:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = g84_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x94:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x96:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x98:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa0:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gt200_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
break;
case 0xaa:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xac:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa3:
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa5:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa8:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xaf:
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
- device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
default:
#include <nvif/event.h>
#include <nvif/unpack.h>
-int
+static void
+nvkm_disp_vblank_fini(struct nvkm_event *event, int type, int head)
+{
+ struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
+ disp->func->head.vblank_fini(disp, head);
+}
+
+static void
+nvkm_disp_vblank_init(struct nvkm_event *event, int type, int head)
+{
+ struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
+ disp->func->head.vblank_init(disp, head);
+}
+
+static int
nvkm_disp_vblank_ctor(struct nvkm_object *object, void *data, u32 size,
struct nvkm_notify *notify)
{
return ret;
}
+static const struct nvkm_event_func
+nvkm_disp_vblank_func = {
+ .ctor = nvkm_disp_vblank_ctor,
+ .init = nvkm_disp_vblank_init,
+ .fini = nvkm_disp_vblank_fini,
+};
+
void
nvkm_disp_vblank(struct nvkm_disp *disp, int head)
{
int
nvkm_disp_ntfy(struct nvkm_object *object, u32 type, struct nvkm_event **event)
{
- struct nvkm_disp *disp = (void *)object->engine;
+ struct nvkm_disp *disp = nvkm_disp(object->engine);
switch (type) {
case NV04_DISP_NTFY_VBLANK:
*event = &disp->vblank;
{
struct nvkm_disp *disp = nvkm_disp(oclass->engine);
if (index == 0) {
- oclass->base = disp->func->root->base;
- oclass->engn = disp->func->root;
+ const struct nvkm_disp_oclass *root = disp->func->root(disp);
+ oclass->base = root->base;
+ oclass->engn = root;
*class = &nvkm_disp_sclass;
return 0;
}
return 1;
}
-int
-_nvkm_disp_fini(struct nvkm_object *object, bool suspend)
+static void
+nvkm_disp_intr(struct nvkm_engine *engine)
+{
+ struct nvkm_disp *disp = nvkm_disp(engine);
+ disp->func->intr(disp);
+}
+
+static int
+nvkm_disp_fini(struct nvkm_engine *engine, bool suspend)
{
- struct nvkm_disp *disp = (void *)object;
+ struct nvkm_disp *disp = nvkm_disp(engine);
struct nvkm_connector *conn;
struct nvkm_output *outp;
nvkm_connector_fini(conn);
}
- return nvkm_engine_fini_old(&disp->engine, suspend);
+ return 0;
}
-int
-_nvkm_disp_init(struct nvkm_object *object)
+static int
+nvkm_disp_init(struct nvkm_engine *engine)
{
- struct nvkm_disp *disp = (void *)object;
+ struct nvkm_disp *disp = nvkm_disp(engine);
struct nvkm_connector *conn;
struct nvkm_output *outp;
- int ret;
-
- ret = nvkm_engine_init_old(&disp->engine);
- if (ret)
- return ret;
list_for_each_entry(conn, &disp->conn, head) {
nvkm_connector_init(conn);
nvkm_output_init(outp);
}
- return ret;
+ return 0;
}
-void
-_nvkm_disp_dtor(struct nvkm_object *object)
+static void *
+nvkm_disp_dtor(struct nvkm_engine *engine)
{
- struct nvkm_disp *disp = (void *)object;
+ struct nvkm_disp *disp = nvkm_disp(engine);
struct nvkm_connector *conn;
struct nvkm_output *outp;
+ void *data = disp;
+
+ if (disp->func->dtor)
+ data = disp->func->dtor(disp);
nvkm_event_fini(&disp->vblank);
nvkm_event_fini(&disp->hpd);
nvkm_connector_del(&conn);
}
- nvkm_engine_destroy(&disp->engine);
+ return data;
}
static const struct nvkm_engine_func
nvkm_disp = {
+ .dtor = nvkm_disp_dtor,
+ .init = nvkm_disp_init,
+ .fini = nvkm_disp_fini,
+ .intr = nvkm_disp_intr,
.base.sclass = nvkm_disp_class_get,
};
int
-nvkm_disp_create_(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, int heads, const char *intname,
- const char *extname, int length, void **pobject)
+nvkm_disp_ctor(const struct nvkm_disp_func *func, struct nvkm_device *device,
+ int index, int heads, struct nvkm_disp *disp)
{
- struct nvkm_disp_impl *impl = (void *)oclass;
- struct nvkm_device *device = (void *)parent;
struct nvkm_bios *bios = device->bios;
- struct nvkm_disp *disp;
- struct nvkm_connector *conn;
struct nvkm_output *outp, *outt, *pair;
+ struct nvkm_connector *conn;
struct nvbios_connE connE;
struct dcb_output dcbE;
u8 hpd = 0, ver, hdr;
u32 data;
int ret, i;
- ret = nvkm_engine_create_(parent, engine, oclass, true, intname,
- extname, length, pobject);
- disp = *pobject;
- if (ret)
- return ret;
-
- disp->engine.func = &nvkm_disp;
INIT_LIST_HEAD(&disp->outp);
INIT_LIST_HEAD(&disp->conn);
+ disp->func = func;
+ disp->head.nr = heads;
+
+ ret = nvkm_engine_ctor(&nvkm_disp, device, index, 0,
+ true, &disp->engine);
+ if (ret)
+ return ret;
/* create output objects for each display path in the vbios */
i = -1;
outp = NULL;
switch (dcbE.location) {
- case 0: outps = &impl->outp.internal; break;
- case 1: outps = &impl->outp.external; break;
+ case 0: outps = &disp->func->outp.internal; break;
+ case 1: outps = &disp->func->outp.external; break;
default:
nvkm_warn(&disp->engine.subdev,
"dcb %d locn %d unknown\n", i, dcbE.location);
if (ret)
return ret;
- ret = nvkm_event_init(impl->vblank, 1, heads, &disp->vblank);
+ ret = nvkm_event_init(&nvkm_disp_vblank_func, 1, heads, &disp->vblank);
if (ret)
return ret;
return 0;
}
+
+int
+nvkm_disp_new_(const struct nvkm_disp_func *func, struct nvkm_device *device,
+ int index, int heads, struct nvkm_disp **pdisp)
+{
+ if (!(*pdisp = kzalloc(sizeof(**pdisp), GFP_KERNEL)))
+ return -ENOMEM;
+ return nvkm_disp_ctor(func, device, index, heads, *pdisp);
+}
nvif_ioctl(parent, "create disp base channel dma vers %d "
"pushbuf %016llx head %d\n",
args->v0.version, args->v0.pushbuf, args->v0.head);
- if (args->v0.head > disp->head.nr)
+ if (args->v0.head > disp->base.head.nr)
return -EINVAL;
push = args->v0.pushbuf;
head = args->v0.head;
if (nvif_unpack(args->v0, 0, 0, false)) {
nvif_ioctl(parent, "create disp cursor vers %d head %d\n",
args->v0.version, args->v0.head);
- if (args->v0.head > disp->head.nr)
+ if (args->v0.head > disp->base.head.nr)
return -EINVAL;
head = args->v0.head;
} else
nvkm_dp_train(struct work_struct *w)
{
struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work);
- struct nv50_disp *disp = (void *)outp->base.disp;
+ struct nv50_disp *disp = nv50_disp(outp->base.disp);
const struct dp_rates *cfg = nvkm_dp_rates;
struct dp_state _dp = {
.outp = outp,
u32 datarate = 0;
int ret;
- if (!outp->base.info.location && disp->sor.magic)
- disp->sor.magic(&outp->base);
+ if (!outp->base.info.location && disp->func->sor.magic)
+ disp->func->sor.magic(&outp->base);
/* bring capabilities within encoder limits */
if (disp->base.engine.subdev.device->chipset < 0xd0)
#include "nv50.h"
#include "rootnv50.h"
-static const struct nvkm_disp_func
+static const struct nv50_disp_func
g84_disp = {
+ .intr = nv50_disp_intr,
+ .uevent = &nv50_disp_chan_uevent,
+ .super = nv50_disp_intr_supervisor,
.root = &g84_disp_root_oclass,
+ .head.vblank_init = nv50_disp_vblank_init,
+ .head.vblank_fini = nv50_disp_vblank_fini,
+ .head.scanoutpos = nv50_disp_root_scanoutpos,
+ .outp.internal.crt = nv50_dac_output_new,
+ .outp.internal.tmds = nv50_sor_output_new,
+ .outp.internal.lvds = nv50_sor_output_new,
+ .outp.external.tmds = nv50_pior_output_new,
+ .outp.external.dp = nv50_pior_dp_new,
+ .dac.nr = 3,
+ .dac.power = nv50_dac_power,
+ .dac.sense = nv50_dac_sense,
+ .sor.nr = 2,
+ .sor.power = nv50_sor_power,
+ .sor.hdmi = g84_hdmi_ctrl,
+ .pior.nr = 3,
+ .pior.power = nv50_pior_power,
};
-static int
-g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+int
+g84_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
{
- struct nv50_disp *disp;
- int ret;
-
- ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
- "display", &disp);
- *pobject = nv_object(disp);
- if (ret)
- return ret;
-
- disp->base.func = &g84_disp;
-
- ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
- if (ret)
- return ret;
-
- nv_subdev(disp)->intr = nv50_disp_intr;
- INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
- disp->head.nr = 2;
- disp->dac.nr = 3;
- disp->sor.nr = 2;
- disp->pior.nr = 3;
- disp->dac.power = nv50_dac_power;
- disp->dac.sense = nv50_dac_sense;
- disp->sor.power = nv50_sor_power;
- disp->sor.hdmi = g84_hdmi_ctrl;
- disp->pior.power = nv50_pior_power;
- return 0;
+ return nv50_disp_new_(&g84_disp, device, index, 2, pdisp);
}
-
-struct nvkm_oclass *
-g84_disp_oclass = &(struct nv50_disp_impl) {
- .base.base.handle = NV_ENGINE(DISP, 0x82),
- .base.base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = g84_disp_ctor,
- .dtor = _nvkm_disp_dtor,
- .init = _nvkm_disp_init,
- .fini = _nvkm_disp_fini,
- },
- .base.outp.internal.crt = nv50_dac_output_new,
- .base.outp.internal.tmds = nv50_sor_output_new,
- .base.outp.internal.lvds = nv50_sor_output_new,
- .base.outp.external.tmds = nv50_pior_output_new,
- .base.outp.external.dp = nv50_pior_dp_new,
- .base.vblank = &nv50_disp_vblank_func,
- .head.scanoutpos = nv50_disp_root_scanoutpos,
-}.base.base;
#include "nv50.h"
#include "rootnv50.h"
-static const struct nvkm_disp_func
+static const struct nv50_disp_func
g94_disp = {
+ .intr = nv50_disp_intr,
+ .uevent = &nv50_disp_chan_uevent,
+ .super = nv50_disp_intr_supervisor,
.root = &g94_disp_root_oclass,
+ .head.vblank_init = nv50_disp_vblank_init,
+ .head.vblank_fini = nv50_disp_vblank_fini,
+ .head.scanoutpos = nv50_disp_root_scanoutpos,
+ .outp.internal.crt = nv50_dac_output_new,
+ .outp.internal.tmds = nv50_sor_output_new,
+ .outp.internal.lvds = nv50_sor_output_new,
+ .outp.internal.dp = g94_sor_dp_new,
+ .outp.external.tmds = nv50_pior_output_new,
+ .outp.external.dp = nv50_pior_dp_new,
+ .dac.nr = 3,
+ .dac.power = nv50_dac_power,
+ .dac.sense = nv50_dac_sense,
+ .sor.nr = 4,
+ .sor.power = nv50_sor_power,
+ .sor.hdmi = g84_hdmi_ctrl,
+ .pior.nr = 3,
+ .pior.power = nv50_pior_power,
};
-static int
-g94_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+int
+g94_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
{
- struct nv50_disp *disp;
- int ret;
-
- ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
- "display", &disp);
- *pobject = nv_object(disp);
- if (ret)
- return ret;
-
- disp->base.func = &g94_disp;
-
- ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
- if (ret)
- return ret;
-
- nv_subdev(disp)->intr = nv50_disp_intr;
- INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
- disp->head.nr = 2;
- disp->dac.nr = 3;
- disp->sor.nr = 4;
- disp->pior.nr = 3;
- disp->dac.power = nv50_dac_power;
- disp->dac.sense = nv50_dac_sense;
- disp->sor.power = nv50_sor_power;
- disp->sor.hdmi = g84_hdmi_ctrl;
- disp->pior.power = nv50_pior_power;
- return 0;
+ return nv50_disp_new_(&g94_disp, device, index, 2, pdisp);
}
-
-struct nvkm_oclass *
-g94_disp_oclass = &(struct nv50_disp_impl) {
- .base.base.handle = NV_ENGINE(DISP, 0x88),
- .base.base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = g94_disp_ctor,
- .dtor = _nvkm_disp_dtor,
- .init = _nvkm_disp_init,
- .fini = _nvkm_disp_fini,
- },
- .base.outp.internal.crt = nv50_dac_output_new,
- .base.outp.internal.tmds = nv50_sor_output_new,
- .base.outp.internal.lvds = nv50_sor_output_new,
- .base.outp.internal.dp = g94_sor_dp_new,
- .base.outp.external.lvds = nv50_pior_output_new,
- .base.outp.external.dp = nv50_pior_dp_new,
- .base.vblank = &nv50_disp_vblank_func,
- .head.scanoutpos = nv50_disp_root_scanoutpos,
-}.base.base;
#include <subdev/bios/pll.h>
#include <subdev/devinit.h>
-static void
-gf119_disp_vblank_init(struct nvkm_event *event, int type, int head)
+void
+gf119_disp_vblank_init(struct nv50_disp *disp, int head)
{
- struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
- struct nvkm_device *device = disp->engine.subdev.device;
+ struct nvkm_device *device = disp->base.engine.subdev.device;
nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001);
}
-static void
-gf119_disp_vblank_fini(struct nvkm_event *event, int type, int head)
+void
+gf119_disp_vblank_fini(struct nv50_disp *disp, int head)
{
- struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
- struct nvkm_device *device = disp->engine.subdev.device;
+ struct nvkm_device *device = disp->base.engine.subdev.device;
nvkm_mask(device, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000);
}
-const struct nvkm_event_func
-gf119_disp_vblank_func = {
- .ctor = nvkm_disp_vblank_ctor,
- .init = gf119_disp_vblank_init,
- .fini = gf119_disp_vblank_fini,
-};
-
static struct nvkm_output *
exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl,
u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
static struct nvkm_output *
exec_script(struct nv50_disp *disp, int head, int id)
{
- struct nvkm_device *device = disp->base.engine.subdev.device;
+ struct nvkm_subdev *subdev = &disp->base.engine.subdev;
+ struct nvkm_device *device = subdev->device;
struct nvkm_bios *bios = device->bios;
struct nvkm_output *outp;
struct nvbios_outp info;
outp = exec_lookup(disp, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info);
if (outp) {
struct nvbios_init init = {
- .subdev = nv_subdev(disp),
+ .subdev = subdev,
.bios = bios,
.offset = info.script[id],
.outp = &outp->info,
static struct nvkm_output *
exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
{
- struct nvkm_device *device = disp->base.engine.subdev.device;
+ struct nvkm_subdev *subdev = &disp->base.engine.subdev;
+ struct nvkm_device *device = subdev->device;
struct nvkm_bios *bios = device->bios;
struct nvkm_output *outp;
struct nvbios_outp info1;
data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
if (data) {
struct nvbios_init init = {
- .subdev = nv_subdev(disp),
+ .subdev = subdev,
.bios = bios,
.offset = data,
.outp = &outp->info,
if (nvkm_output_dp_train(outp, pclk, true))
OUTP_ERR(outp, "link not trained before attach");
} else {
- if (disp->sor.magic)
- disp->sor.magic(outp);
+ if (disp->func->sor.magic)
+ disp->func->sor.magic(outp);
}
exec_clkcmp(disp, head, 0, pclk, &conf);
int head;
nvkm_debug(subdev, "supervisor %d\n", ffs(disp->super));
- for (head = 0; head < disp->head.nr; head++) {
+ for (head = 0; head < disp->base.head.nr; head++) {
mask[head] = nvkm_rd32(device, 0x6101d4 + (head * 0x800));
nvkm_debug(subdev, "head %d: %08x\n", head, mask[head]);
}
if (disp->super & 0x00000001) {
nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG);
- for (head = 0; head < disp->head.nr; head++) {
+ for (head = 0; head < disp->base.head.nr; head++) {
if (!(mask[head] & 0x00001000))
continue;
nvkm_debug(subdev, "supervisor 1.0 - head %d\n", head);
}
} else
if (disp->super & 0x00000002) {
- for (head = 0; head < disp->head.nr; head++) {
+ for (head = 0; head < disp->base.head.nr; head++) {
if (!(mask[head] & 0x00001000))
continue;
nvkm_debug(subdev, "supervisor 2.0 - head %d\n", head);
gf119_disp_intr_unk2_0(disp, head);
}
- for (head = 0; head < disp->head.nr; head++) {
+ for (head = 0; head < disp->base.head.nr; head++) {
if (!(mask[head] & 0x00010000))
continue;
nvkm_debug(subdev, "supervisor 2.1 - head %d\n", head);
gf119_disp_intr_unk2_1(disp, head);
}
- for (head = 0; head < disp->head.nr; head++) {
+ for (head = 0; head < disp->base.head.nr; head++) {
if (!(mask[head] & 0x00001000))
continue;
nvkm_debug(subdev, "supervisor 2.2 - head %d\n", head);
}
} else
if (disp->super & 0x00000004) {
- for (head = 0; head < disp->head.nr; head++) {
+ for (head = 0; head < disp->base.head.nr; head++) {
if (!(mask[head] & 0x00001000))
continue;
nvkm_debug(subdev, "supervisor 3.0 - head %d\n", head);
}
}
- for (head = 0; head < disp->head.nr; head++)
+ for (head = 0; head < disp->base.head.nr; head++)
nvkm_wr32(device, 0x6101d4 + (head * 0x800), 0x00000000);
nvkm_wr32(device, 0x6101d0, 0x80000000);
}
}
void
-gf119_disp_intr(struct nvkm_subdev *subdev)
+gf119_disp_intr(struct nv50_disp *disp)
{
- struct nv50_disp *disp = (void *)subdev;
+ struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_device *device = subdev->device;
u32 intr = nvkm_rd32(device, 0x610088);
int i;
intr &= ~0x00100000;
}
- for (i = 0; i < disp->head.nr; i++) {
+ for (i = 0; i < disp->base.head.nr; i++) {
u32 mask = 0x01000000 << i;
if (mask & intr) {
u32 stat = nvkm_rd32(device, 0x6100bc + (i * 0x800));
}
}
-static const struct nvkm_disp_func
+int
+gf119_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device,
+ int index, struct nvkm_disp **pdisp)
+{
+ u32 heads = nvkm_rd32(device, 0x022448);
+ return nv50_disp_new_(func, device, index, heads, pdisp);
+}
+
+static const struct nv50_disp_func
gf119_disp = {
+ .intr = gf119_disp_intr,
+ .uevent = &gf119_disp_chan_uevent,
+ .super = gf119_disp_intr_supervisor,
.root = &gf119_disp_root_oclass,
+ .head.vblank_init = gf119_disp_vblank_init,
+ .head.vblank_fini = gf119_disp_vblank_fini,
+ .head.scanoutpos = gf119_disp_root_scanoutpos,
+ .outp.internal.crt = nv50_dac_output_new,
+ .outp.internal.tmds = nv50_sor_output_new,
+ .outp.internal.lvds = nv50_sor_output_new,
+ .outp.internal.dp = gf119_sor_dp_new,
+ .dac.nr = 3,
+ .dac.power = nv50_dac_power,
+ .dac.sense = nv50_dac_sense,
+ .sor.nr = 4,
+ .sor.power = nv50_sor_power,
+ .sor.hda_eld = gf119_hda_eld,
+ .sor.hdmi = gf119_hdmi_ctrl,
};
-static int
-gf119_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+int
+gf119_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
{
- struct nvkm_device *device = (void *)parent;
- struct nv50_disp *disp;
- int heads = nvkm_rd32(device, 0x022448);
- int ret;
-
- ret = nvkm_disp_create(parent, engine, oclass, heads,
- "PDISP", "display", &disp);
- *pobject = nv_object(disp);
- if (ret)
- return ret;
-
- disp->base.func = &gf119_disp;
-
- ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
- if (ret)
- return ret;
-
- nv_subdev(disp)->intr = gf119_disp_intr;
- INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
- disp->head.nr = heads;
- disp->dac.nr = 3;
- disp->sor.nr = 4;
- disp->dac.power = nv50_dac_power;
- disp->dac.sense = nv50_dac_sense;
- disp->sor.power = nv50_sor_power;
- disp->sor.hda_eld = gf119_hda_eld;
- disp->sor.hdmi = gf119_hdmi_ctrl;
- return 0;
+ return gf119_disp_new_(&gf119_disp, device, index, pdisp);
}
-
-struct nvkm_oclass *
-gf110_disp_oclass = &(struct nv50_disp_impl) {
- .base.base.handle = NV_ENGINE(DISP, 0x90),
- .base.base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gf119_disp_ctor,
- .dtor = _nvkm_disp_dtor,
- .init = _nvkm_disp_init,
- .fini = _nvkm_disp_fini,
- },
- .base.outp.internal.crt = nv50_dac_output_new,
- .base.outp.internal.tmds = nv50_sor_output_new,
- .base.outp.internal.lvds = nv50_sor_output_new,
- .base.outp.internal.dp = gf119_sor_dp_new,
- .base.vblank = &gf119_disp_vblank_func,
- .head.scanoutpos = gf119_disp_root_scanoutpos,
-}.base.base;
#include "nv50.h"
#include "rootnv50.h"
-static const struct nvkm_disp_func
+static const struct nv50_disp_func
gk104_disp = {
+ .intr = gf119_disp_intr,
+ .uevent = &gf119_disp_chan_uevent,
+ .super = gf119_disp_intr_supervisor,
.root = &gk104_disp_root_oclass,
+ .head.vblank_init = gf119_disp_vblank_init,
+ .head.vblank_fini = gf119_disp_vblank_fini,
+ .head.scanoutpos = gf119_disp_root_scanoutpos,
+ .outp.internal.crt = nv50_dac_output_new,
+ .outp.internal.tmds = nv50_sor_output_new,
+ .outp.internal.lvds = nv50_sor_output_new,
+ .outp.internal.dp = gf119_sor_dp_new,
+ .dac.nr = 3,
+ .dac.power = nv50_dac_power,
+ .dac.sense = nv50_dac_sense,
+ .sor.nr = 4,
+ .sor.power = nv50_sor_power,
+ .sor.hda_eld = gf119_hda_eld,
+ .sor.hdmi = gk104_hdmi_ctrl,
};
-static int
-gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+int
+gk104_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
{
- struct nvkm_device *device = (void *)parent;
- struct nv50_disp *disp;
- int heads = nvkm_rd32(device, 0x022448);
- int ret;
-
- ret = nvkm_disp_create(parent, engine, oclass, heads,
- "PDISP", "display", &disp);
- *pobject = nv_object(disp);
- if (ret)
- return ret;
-
- disp->base.func = &gk104_disp;
-
- ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
- if (ret)
- return ret;
-
- nv_subdev(disp)->intr = gf119_disp_intr;
- INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
- disp->head.nr = heads;
- disp->dac.nr = 3;
- disp->sor.nr = 4;
- disp->dac.power = nv50_dac_power;
- disp->dac.sense = nv50_dac_sense;
- disp->sor.power = nv50_sor_power;
- disp->sor.hda_eld = gf119_hda_eld;
- disp->sor.hdmi = gk104_hdmi_ctrl;
- return 0;
+ return gf119_disp_new_(&gk104_disp, device, index, pdisp);
}
-
-struct nvkm_oclass *
-gk104_disp_oclass = &(struct nv50_disp_impl) {
- .base.base.handle = NV_ENGINE(DISP, 0x91),
- .base.base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gk104_disp_ctor,
- .dtor = _nvkm_disp_dtor,
- .init = _nvkm_disp_init,
- .fini = _nvkm_disp_fini,
- },
- .base.outp.internal.crt = nv50_dac_output_new,
- .base.outp.internal.tmds = nv50_sor_output_new,
- .base.outp.internal.lvds = nv50_sor_output_new,
- .base.outp.internal.dp = gf119_sor_dp_new,
- .base.vblank = &gf119_disp_vblank_func,
- .head.scanoutpos = gf119_disp_root_scanoutpos,
-}.base.base;
#include "nv50.h"
#include "rootnv50.h"
-static const struct nvkm_disp_func
+static const struct nv50_disp_func
gk110_disp = {
+ .intr = gf119_disp_intr,
+ .uevent = &gf119_disp_chan_uevent,
+ .super = gf119_disp_intr_supervisor,
.root = &gk110_disp_root_oclass,
+ .head.vblank_init = gf119_disp_vblank_init,
+ .head.vblank_fini = gf119_disp_vblank_fini,
+ .head.scanoutpos = gf119_disp_root_scanoutpos,
+ .outp.internal.crt = nv50_dac_output_new,
+ .outp.internal.tmds = nv50_sor_output_new,
+ .outp.internal.lvds = nv50_sor_output_new,
+ .outp.internal.dp = gf119_sor_dp_new,
+ .dac.nr = 3,
+ .dac.power = nv50_dac_power,
+ .dac.sense = nv50_dac_sense,
+ .sor.nr = 4,
+ .sor.power = nv50_sor_power,
+ .sor.hda_eld = gf119_hda_eld,
+ .sor.hdmi = gk104_hdmi_ctrl,
};
-static int
-gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+int
+gk110_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
{
- struct nvkm_device *device = (void *)parent;
- struct nv50_disp *disp;
- int heads = nvkm_rd32(device, 0x022448);
- int ret;
-
- ret = nvkm_disp_create(parent, engine, oclass, heads,
- "PDISP", "display", &disp);
- *pobject = nv_object(disp);
- if (ret)
- return ret;
-
- disp->base.func = &gk110_disp;
-
- ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
- if (ret)
- return ret;
-
- nv_subdev(disp)->intr = gf119_disp_intr;
- INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
- disp->head.nr = heads;
- disp->dac.nr = 3;
- disp->sor.nr = 4;
- disp->dac.power = nv50_dac_power;
- disp->dac.sense = nv50_dac_sense;
- disp->sor.power = nv50_sor_power;
- disp->sor.hda_eld = gf119_hda_eld;
- disp->sor.hdmi = gk104_hdmi_ctrl;
- return 0;
+ return gf119_disp_new_(&gk110_disp, device, index, pdisp);
}
-
-struct nvkm_oclass *
-gk110_disp_oclass = &(struct nv50_disp_impl) {
- .base.base.handle = NV_ENGINE(DISP, 0x92),
- .base.base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gk110_disp_ctor,
- .dtor = _nvkm_disp_dtor,
- .init = _nvkm_disp_init,
- .fini = _nvkm_disp_fini,
- },
- .base.outp.internal.crt = nv50_dac_output_new,
- .base.outp.internal.tmds = nv50_sor_output_new,
- .base.outp.internal.lvds = nv50_sor_output_new,
- .base.outp.internal.dp = gf119_sor_dp_new,
- .base.vblank = &gf119_disp_vblank_func,
- .head.scanoutpos = gf119_disp_root_scanoutpos,
-}.base.base;
#include "nv50.h"
#include "rootnv50.h"
-static const struct nvkm_disp_func
+static const struct nv50_disp_func
gm107_disp = {
+ .intr = gf119_disp_intr,
+ .uevent = &gf119_disp_chan_uevent,
+ .super = gf119_disp_intr_supervisor,
.root = &gm107_disp_root_oclass,
+ .head.vblank_init = gf119_disp_vblank_init,
+ .head.vblank_fini = gf119_disp_vblank_fini,
+ .head.scanoutpos = gf119_disp_root_scanoutpos,
+ .outp.internal.crt = nv50_dac_output_new,
+ .outp.internal.tmds = nv50_sor_output_new,
+ .outp.internal.lvds = nv50_sor_output_new,
+ .outp.internal.dp = gf119_sor_dp_new,
+ .dac.nr = 3,
+ .dac.power = nv50_dac_power,
+ .dac.sense = nv50_dac_sense,
+ .sor.nr = 4,
+ .sor.power = nv50_sor_power,
+ .sor.hda_eld = gf119_hda_eld,
+ .sor.hdmi = gk104_hdmi_ctrl,
};
-static int
-gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+int
+gm107_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
{
- struct nvkm_device *device = (void *)parent;
- struct nv50_disp *disp;
- int heads = nvkm_rd32(device, 0x022448);
- int ret;
-
- ret = nvkm_disp_create(parent, engine, oclass, heads,
- "PDISP", "display", &disp);
- *pobject = nv_object(disp);
- if (ret)
- return ret;
-
- disp->base.func = &gm107_disp;
-
- ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
- if (ret)
- return ret;
-
- nv_subdev(disp)->intr = gf119_disp_intr;
- INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
- disp->head.nr = heads;
- disp->dac.nr = 3;
- disp->sor.nr = 4;
- disp->dac.power = nv50_dac_power;
- disp->dac.sense = nv50_dac_sense;
- disp->sor.power = nv50_sor_power;
- disp->sor.hda_eld = gf119_hda_eld;
- disp->sor.hdmi = gk104_hdmi_ctrl;
- return 0;
+ return gf119_disp_new_(&gm107_disp, device, index, pdisp);
}
-
-struct nvkm_oclass *
-gm107_disp_oclass = &(struct nv50_disp_impl) {
- .base.base.handle = NV_ENGINE(DISP, 0x07),
- .base.base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gm107_disp_ctor,
- .dtor = _nvkm_disp_dtor,
- .init = _nvkm_disp_init,
- .fini = _nvkm_disp_fini,
- },
- .base.outp.internal.crt = nv50_dac_output_new,
- .base.outp.internal.tmds = nv50_sor_output_new,
- .base.outp.internal.lvds = nv50_sor_output_new,
- .base.outp.internal.dp = gf119_sor_dp_new,
- .base.vblank = &gf119_disp_vblank_func,
- .head.scanoutpos = gf119_disp_root_scanoutpos,
-}.base.base;
#include "nv50.h"
#include "rootnv50.h"
-static const struct nvkm_disp_func
+static const struct nv50_disp_func
gm204_disp = {
+ .intr = gf119_disp_intr,
+ .uevent = &gf119_disp_chan_uevent,
+ .super = gf119_disp_intr_supervisor,
.root = &gm204_disp_root_oclass,
+ .head.vblank_init = gf119_disp_vblank_init,
+ .head.vblank_fini = gf119_disp_vblank_fini,
+ .head.scanoutpos = gf119_disp_root_scanoutpos,
+ .outp.internal.crt = nv50_dac_output_new,
+ .outp.internal.tmds = nv50_sor_output_new,
+ .outp.internal.lvds = nv50_sor_output_new,
+ .outp.internal.dp = gm204_sor_dp_new,
+ .dac.nr = 3,
+ .dac.power = nv50_dac_power,
+ .dac.sense = nv50_dac_sense,
+ .sor.nr = 4,
+ .sor.power = nv50_sor_power,
+ .sor.hda_eld = gf119_hda_eld,
+ .sor.hdmi = gk104_hdmi_ctrl,
+ .sor.magic = gm204_sor_magic,
};
-static int
-gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+int
+gm204_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
{
- struct nvkm_device *device = (void *)parent;
- struct nv50_disp *disp;
- int heads = nvkm_rd32(device, 0x022448);
- int ret;
-
- ret = nvkm_disp_create(parent, engine, oclass, heads,
- "PDISP", "display", &disp);
- *pobject = nv_object(disp);
- if (ret)
- return ret;
-
- disp->base.func = &gm204_disp;
-
- ret = nvkm_event_init(&gf119_disp_chan_uevent, 1, 17, &disp->uevent);
- if (ret)
- return ret;
-
- nv_subdev(disp)->intr = gf119_disp_intr;
- INIT_WORK(&disp->supervisor, gf119_disp_intr_supervisor);
- disp->head.nr = heads;
- disp->dac.nr = 3;
- disp->sor.nr = 4;
- disp->dac.power = nv50_dac_power;
- disp->dac.sense = nv50_dac_sense;
- disp->sor.power = nv50_sor_power;
- disp->sor.hda_eld = gf119_hda_eld;
- disp->sor.hdmi = gf119_hdmi_ctrl;
- disp->sor.magic = gm204_sor_magic;
- return 0;
+ return gf119_disp_new_(&gm204_disp, device, index, pdisp);
}
-
-struct nvkm_oclass *
-gm204_disp_oclass = &(struct nv50_disp_impl) {
- .base.base.handle = NV_ENGINE(DISP, 0x07),
- .base.base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gm204_disp_ctor,
- .dtor = _nvkm_disp_dtor,
- .init = _nvkm_disp_init,
- .fini = _nvkm_disp_fini,
- },
- .base.outp.internal.crt = nv50_dac_output_new,
- .base.outp.internal.tmds = nv50_sor_output_new,
- .base.outp.internal.lvds = nv50_sor_output_new,
- .base.outp.internal.dp = gm204_sor_dp_new,
- .base.vblank = &gf119_disp_vblank_func,
- .head.scanoutpos = gf119_disp_root_scanoutpos,
-}.base.base;
#include "nv50.h"
#include "rootnv50.h"
-static const struct nvkm_disp_func
+static const struct nv50_disp_func
gt200_disp = {
+ .intr = nv50_disp_intr,
+ .uevent = &nv50_disp_chan_uevent,
+ .super = nv50_disp_intr_supervisor,
.root = >200_disp_root_oclass,
+ .head.vblank_init = nv50_disp_vblank_init,
+ .head.vblank_fini = nv50_disp_vblank_fini,
+ .head.scanoutpos = nv50_disp_root_scanoutpos,
+ .outp.internal.crt = nv50_dac_output_new,
+ .outp.internal.tmds = nv50_sor_output_new,
+ .outp.internal.lvds = nv50_sor_output_new,
+ .outp.external.tmds = nv50_pior_output_new,
+ .outp.external.dp = nv50_pior_dp_new,
+ .dac.nr = 3,
+ .dac.power = nv50_dac_power,
+ .dac.sense = nv50_dac_sense,
+ .sor.nr = 2,
+ .sor.power = nv50_sor_power,
+ .sor.hdmi = g84_hdmi_ctrl,
+ .pior.nr = 3,
+ .pior.power = nv50_pior_power,
};
-static int
-gt200_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+int
+gt200_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
{
- struct nv50_disp *disp;
- int ret;
-
- ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
- "display", &disp);
- *pobject = nv_object(disp);
- if (ret)
- return ret;
-
- disp->base.func = >200_disp;
-
- ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
- if (ret)
- return ret;
-
- nv_subdev(disp)->intr = nv50_disp_intr;
- INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
- disp->head.nr = 2;
- disp->dac.nr = 3;
- disp->sor.nr = 2;
- disp->pior.nr = 3;
- disp->dac.power = nv50_dac_power;
- disp->dac.sense = nv50_dac_sense;
- disp->sor.power = nv50_sor_power;
- disp->sor.hdmi = g84_hdmi_ctrl;
- disp->pior.power = nv50_pior_power;
- return 0;
+ return nv50_disp_new_(>200_disp, device, index, 2, pdisp);
}
-
-struct nvkm_oclass *
-gt200_disp_oclass = &(struct nv50_disp_impl) {
- .base.base.handle = NV_ENGINE(DISP, 0x83),
- .base.base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gt200_disp_ctor,
- .dtor = _nvkm_disp_dtor,
- .init = _nvkm_disp_init,
- .fini = _nvkm_disp_fini,
- },
- .base.outp.internal.crt = nv50_dac_output_new,
- .base.outp.internal.tmds = nv50_sor_output_new,
- .base.outp.internal.lvds = nv50_sor_output_new,
- .base.outp.external.tmds = nv50_pior_output_new,
- .base.outp.external.dp = nv50_pior_dp_new,
- .base.vblank = &nv50_disp_vblank_func,
- .head.scanoutpos = nv50_disp_root_scanoutpos,
-}.base.base;
#include "nv50.h"
#include "rootnv50.h"
-static const struct nvkm_disp_func
-gt215_disp_func = {
+static const struct nv50_disp_func
+gt215_disp = {
+ .intr = nv50_disp_intr,
+ .uevent = &nv50_disp_chan_uevent,
+ .super = nv50_disp_intr_supervisor,
.root = >215_disp_root_oclass,
+ .head.vblank_init = nv50_disp_vblank_init,
+ .head.vblank_fini = nv50_disp_vblank_fini,
+ .head.scanoutpos = nv50_disp_root_scanoutpos,
+ .outp.internal.crt = nv50_dac_output_new,
+ .outp.internal.tmds = nv50_sor_output_new,
+ .outp.internal.lvds = nv50_sor_output_new,
+ .outp.internal.dp = g94_sor_dp_new,
+ .outp.external.tmds = nv50_pior_output_new,
+ .outp.external.dp = nv50_pior_dp_new,
+ .dac.nr = 3,
+ .dac.power = nv50_dac_power,
+ .dac.sense = nv50_dac_sense,
+ .sor.nr = 4,
+ .sor.power = nv50_sor_power,
+ .sor.hda_eld = gt215_hda_eld,
+ .sor.hdmi = gt215_hdmi_ctrl,
+ .pior.nr = 3,
+ .pior.power = nv50_pior_power,
};
-static int
-gt215_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+int
+gt215_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
{
- struct nv50_disp *disp;
- int ret;
-
- ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
- "display", &disp);
- *pobject = nv_object(disp);
- if (ret)
- return ret;
-
- disp->base.func = >215_disp_func;
-
- ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
- if (ret)
- return ret;
-
- nv_subdev(disp)->intr = nv50_disp_intr;
- INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
- disp->head.nr = 2;
- disp->dac.nr = 3;
- disp->sor.nr = 4;
- disp->pior.nr = 3;
- disp->dac.power = nv50_dac_power;
- disp->dac.sense = nv50_dac_sense;
- disp->sor.power = nv50_sor_power;
- disp->sor.hda_eld = gt215_hda_eld;
- disp->sor.hdmi = gt215_hdmi_ctrl;
- disp->pior.power = nv50_pior_power;
- return 0;
+ return nv50_disp_new_(>215_disp, device, index, 2, pdisp);
}
-
-struct nvkm_oclass *
-gt215_disp_oclass = &(struct nv50_disp_impl) {
- .base.base.handle = NV_ENGINE(DISP, 0x85),
- .base.base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = gt215_disp_ctor,
- .dtor = _nvkm_disp_dtor,
- .init = _nvkm_disp_init,
- .fini = _nvkm_disp_fini,
- },
- .base.outp.internal.crt = nv50_dac_output_new,
- .base.outp.internal.tmds = nv50_sor_output_new,
- .base.outp.internal.lvds = nv50_sor_output_new,
- .base.outp.internal.dp = g94_sor_dp_new,
- .base.outp.external.lvds = nv50_pior_output_new,
- .base.outp.external.dp = nv50_pior_dp_new,
- .base.vblank = &nv50_disp_vblank_func,
- .head.scanoutpos = nv50_disp_root_scanoutpos,
-}.base.base;
*/
#include "priv.h"
+static const struct nvkm_disp_oclass *
+nv04_disp_root(struct nvkm_disp *disp)
+{
+ return &nv04_disp_root_oclass;
+}
+
static void
-nv04_disp_vblank_init(struct nvkm_event *event, int type, int head)
+nv04_disp_vblank_init(struct nvkm_disp *disp, int head)
{
- struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
struct nvkm_device *device = disp->engine.subdev.device;
nvkm_wr32(device, 0x600140 + (head * 0x2000) , 0x00000001);
}
static void
-nv04_disp_vblank_fini(struct nvkm_event *event, int type, int head)
+nv04_disp_vblank_fini(struct nvkm_disp *disp, int head)
{
- struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
struct nvkm_device *device = disp->engine.subdev.device;
nvkm_wr32(device, 0x600140 + (head * 0x2000) , 0x00000000);
}
-static const struct nvkm_event_func
-nv04_disp_vblank_func = {
- .ctor = nvkm_disp_vblank_ctor,
- .init = nv04_disp_vblank_init,
- .fini = nv04_disp_vblank_fini,
-};
-
static void
-nv04_disp_intr(struct nvkm_subdev *subdev)
+nv04_disp_intr(struct nvkm_disp *disp)
{
- struct nvkm_disp *disp = (void *)subdev;
- struct nvkm_device *device = disp->engine.subdev.device;
+ struct nvkm_subdev *subdev = &disp->engine.subdev;
+ struct nvkm_device *device = subdev->device;
u32 crtc0 = nvkm_rd32(device, 0x600100);
u32 crtc1 = nvkm_rd32(device, 0x602100);
u32 pvideo;
nvkm_wr32(device, 0x602100, 0x00000001);
}
- if (nv_device(disp)->chipset >= 0x10 &&
- nv_device(disp)->chipset <= 0x40) {
+ if (device->chipset >= 0x10 && device->chipset <= 0x40) {
pvideo = nvkm_rd32(device, 0x8100);
if (pvideo & ~0x11)
nvkm_info(subdev, "PVIDEO intr: %08x\n", pvideo);
static const struct nvkm_disp_func
nv04_disp = {
- .root = &nv04_disp_root_oclass,
+ .intr = nv04_disp_intr,
+ .root = nv04_disp_root,
+ .head.vblank_init = nv04_disp_vblank_init,
+ .head.vblank_fini = nv04_disp_vblank_fini,
};
-static int
-nv04_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+int
+nv04_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
{
- struct nvkm_disp *disp;
- int ret;
-
- ret = nvkm_disp_create(parent, engine, oclass, 2, "DISPLAY",
- "display", &disp);
- *pobject = nv_object(disp);
- if (ret)
- return ret;
-
- disp->func = &nv04_disp;
-
- nv_subdev(disp)->intr = nv04_disp_intr;
- return 0;
+ return nvkm_disp_new_(&nv04_disp, device, index, 2, pdisp);
}
-
-struct nvkm_oclass *
-nv04_disp_oclass = &(struct nvkm_disp_impl) {
- .base.handle = NV_ENGINE(DISP, 0x04),
- .base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = nv04_disp_ctor,
- .dtor = _nvkm_disp_dtor,
- .init = _nvkm_disp_init,
- .fini = _nvkm_disp_fini,
- },
- .vblank = &nv04_disp_vblank_func,
-}.base;
#include <subdev/bios/pll.h>
#include <subdev/devinit.h>
+static const struct nvkm_disp_oclass *
+nv50_disp_root_(struct nvkm_disp *base)
+{
+ return nv50_disp(base)->func->root;
+}
+
+static int
+nv50_disp_outp_internal_crt_(struct nvkm_disp *base, int index,
+ struct dcb_output *dcb, struct nvkm_output **poutp)
+{
+ struct nv50_disp *disp = nv50_disp(base);
+ return disp->func->outp.internal.crt(base, index, dcb, poutp);
+}
+
+static int
+nv50_disp_outp_internal_tmds_(struct nvkm_disp *base, int index,
+ struct dcb_output *dcb,
+ struct nvkm_output **poutp)
+{
+ struct nv50_disp *disp = nv50_disp(base);
+ return disp->func->outp.internal.tmds(base, index, dcb, poutp);
+}
+
+static int
+nv50_disp_outp_internal_lvds_(struct nvkm_disp *base, int index,
+ struct dcb_output *dcb,
+ struct nvkm_output **poutp)
+{
+ struct nv50_disp *disp = nv50_disp(base);
+ return disp->func->outp.internal.lvds(base, index, dcb, poutp);
+}
+
+static int
+nv50_disp_outp_internal_dp_(struct nvkm_disp *base, int index,
+ struct dcb_output *dcb, struct nvkm_output **poutp)
+{
+ struct nv50_disp *disp = nv50_disp(base);
+ if (disp->func->outp.internal.dp)
+ return disp->func->outp.internal.dp(base, index, dcb, poutp);
+ return -ENODEV;
+}
+
+static int
+nv50_disp_outp_external_tmds_(struct nvkm_disp *base, int index,
+ struct dcb_output *dcb,
+ struct nvkm_output **poutp)
+{
+ struct nv50_disp *disp = nv50_disp(base);
+ if (disp->func->outp.external.tmds)
+ return disp->func->outp.external.tmds(base, index, dcb, poutp);
+ return -ENODEV;
+}
+
+static int
+nv50_disp_outp_external_dp_(struct nvkm_disp *base, int index,
+ struct dcb_output *dcb, struct nvkm_output **poutp)
+{
+ struct nv50_disp *disp = nv50_disp(base);
+ if (disp->func->outp.external.dp)
+ return disp->func->outp.external.dp(base, index, dcb, poutp);
+ return -ENODEV;
+}
+
static void
-nv50_disp_vblank_fini(struct nvkm_event *event, int type, int head)
+nv50_disp_vblank_fini_(struct nvkm_disp *base, int head)
{
- struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
- struct nvkm_device *device = disp->engine.subdev.device;
- nvkm_mask(device, 0x61002c, (4 << head), 0);
+ struct nv50_disp *disp = nv50_disp(base);
+ disp->func->head.vblank_fini(disp, head);
}
static void
-nv50_disp_vblank_init(struct nvkm_event *event, int type, int head)
+nv50_disp_vblank_init_(struct nvkm_disp *base, int head)
{
- struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
- struct nvkm_device *device = disp->engine.subdev.device;
- nvkm_mask(device, 0x61002c, (4 << head), (4 << head));
+ struct nv50_disp *disp = nv50_disp(base);
+ disp->func->head.vblank_init(disp, head);
+}
+
+static void
+nv50_disp_intr_(struct nvkm_disp *base)
+{
+ struct nv50_disp *disp = nv50_disp(base);
+ disp->func->intr(disp);
+}
+
+static void *
+nv50_disp_dtor_(struct nvkm_disp *base)
+{
+ struct nv50_disp *disp = nv50_disp(base);
+ nvkm_event_fini(&disp->uevent);
+ return disp;
}
-const struct nvkm_event_func
-nv50_disp_vblank_func = {
- .ctor = nvkm_disp_vblank_ctor,
- .init = nv50_disp_vblank_init,
- .fini = nv50_disp_vblank_fini,
+static const struct nvkm_disp_func
+nv50_disp_ = {
+ .dtor = nv50_disp_dtor_,
+ .intr = nv50_disp_intr_,
+ .root = nv50_disp_root_,
+ .outp.internal.crt = nv50_disp_outp_internal_crt_,
+ .outp.internal.tmds = nv50_disp_outp_internal_tmds_,
+ .outp.internal.lvds = nv50_disp_outp_internal_lvds_,
+ .outp.internal.dp = nv50_disp_outp_internal_dp_,
+ .outp.external.tmds = nv50_disp_outp_external_tmds_,
+ .outp.external.dp = nv50_disp_outp_external_dp_,
+ .head.vblank_init = nv50_disp_vblank_init_,
+ .head.vblank_fini = nv50_disp_vblank_fini_,
};
+int
+nv50_disp_new_(const struct nv50_disp_func *func, struct nvkm_device *device,
+ int index, int heads, struct nvkm_disp **pdisp)
+{
+ struct nv50_disp *disp;
+ int ret;
+
+ if (!(disp = kzalloc(sizeof(*disp), GFP_KERNEL)))
+ return -ENOMEM;
+ INIT_WORK(&disp->supervisor, func->super);
+ disp->func = func;
+ *pdisp = &disp->base;
+
+ ret = nvkm_disp_ctor(&nv50_disp_, device, index, heads, &disp->base);
+ if (ret)
+ return ret;
+
+ return nvkm_event_init(func->uevent, 1, 1 + (heads * 4), &disp->uevent);
+}
+
+void
+nv50_disp_vblank_fini(struct nv50_disp *disp, int head)
+{
+ struct nvkm_device *device = disp->base.engine.subdev.device;
+ nvkm_mask(device, 0x61002c, (4 << head), 0);
+}
+
+void
+nv50_disp_vblank_init(struct nv50_disp *disp, int head)
+{
+ struct nvkm_device *device = disp->base.engine.subdev.device;
+ nvkm_mask(device, 0x61002c, (4 << head), (4 << head));
+}
+
static const struct nvkm_enum
nv50_disp_intr_error_type[] = {
{ 3, "ILLEGAL_MTHD" },
static struct nvkm_output *
exec_script(struct nv50_disp *disp, int head, int id)
{
- struct nvkm_device *device = disp->base.engine.subdev.device;
+ struct nvkm_subdev *subdev = &disp->base.engine.subdev;
+ struct nvkm_device *device = subdev->device;
struct nvkm_bios *bios = device->bios;
struct nvkm_output *outp;
struct nvbios_outp info;
int i;
/* DAC */
- for (i = 0; !(ctrl & (1 << head)) && i < disp->dac.nr; i++)
+ for (i = 0; !(ctrl & (1 << head)) && i < disp->func->dac.nr; i++)
ctrl = nvkm_rd32(device, 0x610b5c + (i * 8));
/* SOR */
if (!(ctrl & (1 << head))) {
- if (nv_device(disp)->chipset < 0x90 ||
- nv_device(disp)->chipset == 0x92 ||
- nv_device(disp)->chipset == 0xa0) {
+ if (device->chipset < 0x90 ||
+ device->chipset == 0x92 ||
+ device->chipset == 0xa0) {
reg = 0x610b74;
} else {
reg = 0x610798;
}
- for (i = 0; !(ctrl & (1 << head)) && i < disp->sor.nr; i++)
+ for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++)
ctrl = nvkm_rd32(device, reg + (i * 8));
i += 4;
}
/* PIOR */
if (!(ctrl & (1 << head))) {
- for (i = 0; !(ctrl & (1 << head)) && i < disp->pior.nr; i++)
+ for (i = 0; !(ctrl & (1 << head)) && i < disp->func->pior.nr; i++)
ctrl = nvkm_rd32(device, 0x610b84 + (i * 8));
i += 8;
}
outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info);
if (outp) {
struct nvbios_init init = {
- .subdev = nv_subdev(disp),
+ .subdev = subdev,
.bios = bios,
.offset = info.script[id],
.outp = &outp->info,
static struct nvkm_output *
exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf)
{
- struct nvkm_device *device = disp->base.engine.subdev.device;
+ struct nvkm_subdev *subdev = &disp->base.engine.subdev;
+ struct nvkm_device *device = subdev->device;
struct nvkm_bios *bios = device->bios;
struct nvkm_output *outp;
struct nvbios_outp info1;
int i;
/* DAC */
- for (i = 0; !(ctrl & (1 << head)) && i < disp->dac.nr; i++)
+ for (i = 0; !(ctrl & (1 << head)) && i < disp->func->dac.nr; i++)
ctrl = nvkm_rd32(device, 0x610b58 + (i * 8));
/* SOR */
if (!(ctrl & (1 << head))) {
- if (nv_device(disp)->chipset < 0x90 ||
- nv_device(disp)->chipset == 0x92 ||
- nv_device(disp)->chipset == 0xa0) {
+ if (device->chipset < 0x90 ||
+ device->chipset == 0x92 ||
+ device->chipset == 0xa0) {
reg = 0x610b70;
} else {
reg = 0x610794;
}
- for (i = 0; !(ctrl & (1 << head)) && i < disp->sor.nr; i++)
+ for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++)
ctrl = nvkm_rd32(device, reg + (i * 8));
i += 4;
}
/* PIOR */
if (!(ctrl & (1 << head))) {
- for (i = 0; !(ctrl & (1 << head)) && i < disp->pior.nr; i++)
+ for (i = 0; !(ctrl & (1 << head)) && i < disp->func->pior.nr; i++)
ctrl = nvkm_rd32(device, 0x610b80 + (i * 8));
i += 8;
}
data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
if (data) {
struct nvbios_init init = {
- .subdev = nv_subdev(disp),
+ .subdev = subdev,
.bios = bios,
.offset = data,
.outp = &outp->info,
if (disp->super & 0x00000010) {
nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG);
- for (head = 0; head < disp->head.nr; head++) {
+ for (head = 0; head < disp->base.head.nr; head++) {
if (!(super & (0x00000020 << head)))
continue;
if (!(super & (0x00000080 << head)))
}
} else
if (disp->super & 0x00000020) {
- for (head = 0; head < disp->head.nr; head++) {
+ for (head = 0; head < disp->base.head.nr; head++) {
if (!(super & (0x00000080 << head)))
continue;
nv50_disp_intr_unk20_0(disp, head);
}
- for (head = 0; head < disp->head.nr; head++) {
+ for (head = 0; head < disp->base.head.nr; head++) {
if (!(super & (0x00000200 << head)))
continue;
nv50_disp_intr_unk20_1(disp, head);
}
- for (head = 0; head < disp->head.nr; head++) {
+ for (head = 0; head < disp->base.head.nr; head++) {
if (!(super & (0x00000080 << head)))
continue;
nv50_disp_intr_unk20_2(disp, head);
}
} else
if (disp->super & 0x00000040) {
- for (head = 0; head < disp->head.nr; head++) {
+ for (head = 0; head < disp->base.head.nr; head++) {
if (!(super & (0x00000080 << head)))
continue;
nv50_disp_intr_unk40_0(disp, head);
}
void
-nv50_disp_intr(struct nvkm_subdev *subdev)
+nv50_disp_intr(struct nv50_disp *disp)
{
- struct nv50_disp *disp = (void *)subdev;
struct nvkm_device *device = disp->base.engine.subdev.device;
u32 intr0 = nvkm_rd32(device, 0x610020);
u32 intr1 = nvkm_rd32(device, 0x610024);
}
}
-static const struct nvkm_disp_func
+static const struct nv50_disp_func
nv50_disp = {
+ .intr = nv50_disp_intr,
+ .uevent = &nv50_disp_chan_uevent,
+ .super = nv50_disp_intr_supervisor,
.root = &nv50_disp_root_oclass,
+ .head.vblank_init = nv50_disp_vblank_init,
+ .head.vblank_fini = nv50_disp_vblank_fini,
+ .head.scanoutpos = nv50_disp_root_scanoutpos,
+ .outp.internal.crt = nv50_dac_output_new,
+ .outp.internal.tmds = nv50_sor_output_new,
+ .outp.internal.lvds = nv50_sor_output_new,
+ .outp.external.tmds = nv50_pior_output_new,
+ .outp.external.dp = nv50_pior_dp_new,
+ .dac.nr = 3,
+ .dac.power = nv50_dac_power,
+ .dac.sense = nv50_dac_sense,
+ .sor.nr = 2,
+ .sor.power = nv50_sor_power,
+ .pior.nr = 3,
+ .pior.power = nv50_pior_power,
};
-static int
-nv50_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+int
+nv50_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
{
- struct nv50_disp *disp;
- int ret;
-
- ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
- "display", &disp);
- *pobject = nv_object(disp);
- if (ret)
- return ret;
-
- disp->base.func = &nv50_disp;
-
- ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent);
- if (ret)
- return ret;
-
- nv_subdev(disp)->intr = nv50_disp_intr;
- INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor);
- disp->head.nr = 2;
- disp->dac.nr = 3;
- disp->sor.nr = 2;
- disp->pior.nr = 3;
- disp->dac.power = nv50_dac_power;
- disp->dac.sense = nv50_dac_sense;
- disp->sor.power = nv50_sor_power;
- disp->pior.power = nv50_pior_power;
- return 0;
+ return nv50_disp_new_(&nv50_disp, device, index, 2, pdisp);
}
-
-struct nvkm_oclass *
-nv50_disp_oclass = &(struct nv50_disp_impl) {
- .base.base.handle = NV_ENGINE(DISP, 0x50),
- .base.base.ofuncs = &(struct nvkm_ofuncs) {
- .ctor = nv50_disp_ctor,
- .dtor = _nvkm_disp_dtor,
- .init = _nvkm_disp_init,
- .fini = _nvkm_disp_fini,
- },
- .base.outp.internal.crt = nv50_dac_output_new,
- .base.outp.internal.tmds = nv50_sor_output_new,
- .base.outp.internal.lvds = nv50_sor_output_new,
- .base.outp.external.tmds = nv50_pior_output_new,
- .base.outp.external.dp = nv50_pior_dp_new,
- .base.vblank = &nv50_disp_vblank_func,
- .head.scanoutpos = nv50_disp_root_scanoutpos,
-}.base.base;
#define NV50_DISP_MTHD_V1 NV50_DISP_MTHD_, int head, struct nvkm_output *outp
struct nv50_disp {
+ const struct nv50_disp_func *func;
struct nvkm_disp base;
struct work_struct supervisor;
struct nvkm_event uevent;
struct {
- int nr;
- } head;
- struct {
- int nr;
- int (*power)(NV50_DISP_MTHD_V1);
- int (*sense)(NV50_DISP_MTHD_V1);
- } dac;
- struct {
- int nr;
- int (*power)(NV50_DISP_MTHD_V1);
- int (*hda_eld)(NV50_DISP_MTHD_V1);
- int (*hdmi)(NV50_DISP_MTHD_V1);
u32 lvdsconf;
- void (*magic)(struct nvkm_output *);
} sor;
+
struct {
- int nr;
- int (*power)(NV50_DISP_MTHD_V1);
u8 type[3];
} pior;
struct nv50_disp_chan *chan[17];
};
-struct nv50_disp_impl {
- struct nvkm_disp_impl base;
- struct {
- int (*scanoutpos)(NV50_DISP_MTHD_V0);
- } head;
-};
-
int nv50_disp_root_scanoutpos(NV50_DISP_MTHD_V0);
int gf119_disp_root_scanoutpos(NV50_DISP_MTHD_V0);
int nv50_sor_power(NV50_DISP_MTHD_V1);
int nv50_pior_power(NV50_DISP_MTHD_V1);
+int nv50_disp_new_(const struct nv50_disp_func *, struct nvkm_device *,
+ int index, int heads, struct nvkm_disp **);
+int gf119_disp_new_(const struct nv50_disp_func *, struct nvkm_device *,
+ int index, struct nvkm_disp **);
+
+struct nv50_disp_func_outp {
+ int (* crt)(struct nvkm_disp *, int index, struct dcb_output *,
+ struct nvkm_output **);
+ int (* tv)(struct nvkm_disp *, int index, struct dcb_output *,
+ struct nvkm_output **);
+ int (*tmds)(struct nvkm_disp *, int index, struct dcb_output *,
+ struct nvkm_output **);
+ int (*lvds)(struct nvkm_disp *, int index, struct dcb_output *,
+ struct nvkm_output **);
+ int (* dp)(struct nvkm_disp *, int index, struct dcb_output *,
+ struct nvkm_output **);
+};
+
+struct nv50_disp_func {
+ void (*intr)(struct nv50_disp *);
+
+ const struct nvkm_event_func *uevent;
+ void (*super)(struct work_struct *);
+
+ const struct nvkm_disp_oclass *root;
+
+ struct {
+ void (*vblank_init)(struct nv50_disp *, int head);
+ void (*vblank_fini)(struct nv50_disp *, int head);
+ int (*scanoutpos)(NV50_DISP_MTHD_V0);
+ } head;
+
+ struct {
+ const struct nv50_disp_func_outp internal;
+ const struct nv50_disp_func_outp external;
+ } outp;
+
+ struct {
+ int nr;
+ int (*power)(NV50_DISP_MTHD_V1);
+ int (*sense)(NV50_DISP_MTHD_V1);
+ } dac;
+
+ struct {
+ int nr;
+ int (*power)(NV50_DISP_MTHD_V1);
+ int (*hda_eld)(NV50_DISP_MTHD_V1);
+ int (*hdmi)(NV50_DISP_MTHD_V1);
+ void (*magic)(struct nvkm_output *);
+ } sor;
+
+ struct {
+ int nr;
+ int (*power)(NV50_DISP_MTHD_V1);
+ } pior;
+};
+
+void nv50_disp_vblank_init(struct nv50_disp *, int);
+void nv50_disp_vblank_fini(struct nv50_disp *, int);
+void nv50_disp_intr(struct nv50_disp *);
void nv50_disp_intr_supervisor(struct work_struct *);
-void nv50_disp_intr(struct nvkm_subdev *);
-extern const struct nvkm_event_func nv50_disp_vblank_func;
+void gf119_disp_vblank_init(struct nv50_disp *, int);
+void gf119_disp_vblank_fini(struct nv50_disp *, int);
+void gf119_disp_intr(struct nv50_disp *);
void gf119_disp_intr_supervisor(struct work_struct *);
-void gf119_disp_intr(struct nvkm_subdev *);
-extern const struct nvkm_event_func gf119_disp_vblank_func;
#endif
if (nvif_unpack(args->v0, 0, 0, false)) {
nvif_ioctl(parent, "create disp overlay vers %d head %d\n",
args->v0.version, args->v0.head);
- if (args->v0.head > disp->head.nr)
+ if (args->v0.head > disp->base.head.nr)
return -EINVAL;
head = args->v0.head;
} else
nvif_ioctl(parent, "create disp overlay channel dma vers %d "
"pushbuf %016llx head %d\n",
args->v0.version, args->v0.pushbuf, args->v0.head);
- if (args->v0.head > disp->head.nr)
+ if (args->v0.head > disp->base.head.nr)
return -EINVAL;
push = args->v0.pushbuf;
head = args->v0.head;
#include "outp.h"
#include "outpdp.h"
+int nvkm_disp_ctor(const struct nvkm_disp_func *, struct nvkm_device *,
+ int index, int heads, struct nvkm_disp *);
+int nvkm_disp_new_(const struct nvkm_disp_func *, struct nvkm_device *,
+ int index, int heads, struct nvkm_disp **);
+void nvkm_disp_vblank(struct nvkm_disp *, int head);
+
struct nvkm_disp_func_outp {
int (* crt)(struct nvkm_disp *, int index, struct dcb_output *,
struct nvkm_output **);
struct nvkm_output **);
};
-struct nvkm_disp_impl {
- struct nvkm_oclass base;
+struct nvkm_disp_func {
+ void *(*dtor)(struct nvkm_disp *);
+ void (*intr)(struct nvkm_disp *);
+
+ const struct nvkm_disp_oclass *(*root)(struct nvkm_disp *);
+
+ struct {
+ void (*vblank_init)(struct nvkm_disp *, int head);
+ void (*vblank_fini)(struct nvkm_disp *, int head);
+ } head;
+
struct {
const struct nvkm_disp_func_outp internal;
const struct nvkm_disp_func_outp external;
} outp;
- const struct nvkm_event_func *vblank;
};
-#define nvkm_disp_create(p,e,c,h,i,x,d) \
- nvkm_disp_create_((p), (e), (c), (h), (i), (x), \
- sizeof(**d), (void **)d)
-#define nvkm_disp_destroy(d) ({ \
- struct nvkm_disp *disp = (d); \
- _nvkm_disp_dtor(nv_object(disp)); \
-})
-#define nvkm_disp_init(d) ({ \
- struct nvkm_disp *disp = (d); \
- _nvkm_disp_init(nv_object(disp)); \
-})
-#define nvkm_disp_fini(d,s) ({ \
- struct nvkm_disp *disp = (d); \
- _nvkm_disp_fini(nv_object(disp), (s)); \
-})
-
-int nvkm_disp_create_(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, int heads,
- const char *, const char *, int, void **);
-void _nvkm_disp_dtor(struct nvkm_object *);
-int _nvkm_disp_init(struct nvkm_object *);
-int _nvkm_disp_fini(struct nvkm_object *, bool);
-
-extern struct nvkm_oclass *nvkm_output_oclass;
-extern struct nvkm_oclass *nvkm_connector_oclass;
-
-int nvkm_disp_vblank_ctor(struct nvkm_object *, void *data, u32 size,
- struct nvkm_notify *);
-void nvkm_disp_vblank(struct nvkm_disp *, int head);
int nvkm_disp_ntfy(struct nvkm_object *, u32, struct nvkm_event **);
extern const struct nvkm_disp_oclass nv04_disp_root_oclass;
*/
/* ... CRTC caps */
- for (i = 0; i < disp->head.nr; i++) {
+ for (i = 0; i < disp->base.head.nr; i++) {
tmp = nvkm_rd32(device, 0x616104 + (i * 0x800));
nvkm_wr32(device, 0x6101b4 + (i * 0x800), tmp);
tmp = nvkm_rd32(device, 0x616108 + (i * 0x800));
}
/* ... DAC caps */
- for (i = 0; i < disp->dac.nr; i++) {
+ for (i = 0; i < disp->func->dac.nr; i++) {
tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800));
nvkm_wr32(device, 0x6101c0 + (i * 0x800), tmp);
}
/* ... SOR caps */
- for (i = 0; i < disp->sor.nr; i++) {
+ for (i = 0; i < disp->func->sor.nr; i++) {
tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
nvkm_wr32(device, 0x6301c4 + (i * 0x800), tmp);
}
*
* ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
*/
- for (i = 0; i < disp->head.nr; i++)
+ for (i = 0; i < disp->base.head.nr; i++)
nvkm_mask(device, 0x616308 + (i * 0x800), 0x00000111, 0x00000010);
return 0;
} *args = data;
struct nv50_disp_root *root = nv50_disp_root(object);
struct nv50_disp *disp = root->disp;
- const struct nv50_disp_impl *impl = (void *)nv_oclass(object->engine);
+ const struct nv50_disp_func *func = disp->func;
struct nvkm_output *outp = NULL;
struct nvkm_output *temp;
u16 type, mask = 0;
} else
return ret;
- if (head < 0 || head >= disp->head.nr)
+ if (head < 0 || head >= disp->base.head.nr)
return -ENXIO;
if (mask) {
switch (mthd) {
case NV50_DISP_SCANOUTPOS:
- return impl->head.scanoutpos(object, disp, data, size, head);
+ return func->head.scanoutpos(object, disp, data, size, head);
default:
break;
}
switch (mthd * !!outp) {
case NV50_DISP_MTHD_V1_DAC_PWR:
- return disp->dac.power(object, disp, data, size, head, outp);
+ return func->dac.power(object, disp, data, size, head, outp);
case NV50_DISP_MTHD_V1_DAC_LOAD:
- return disp->dac.sense(object, disp, data, size, head, outp);
+ return func->dac.sense(object, disp, data, size, head, outp);
case NV50_DISP_MTHD_V1_SOR_PWR:
- return disp->sor.power(object, disp, data, size, head, outp);
+ return func->sor.power(object, disp, data, size, head, outp);
case NV50_DISP_MTHD_V1_SOR_HDA_ELD:
- if (!disp->sor.hda_eld)
+ if (!func->sor.hda_eld)
return -ENODEV;
- return disp->sor.hda_eld(object, disp, data, size, head, outp);
+ return func->sor.hda_eld(object, disp, data, size, head, outp);
case NV50_DISP_MTHD_V1_SOR_HDMI_PWR:
- if (!disp->sor.hdmi)
+ if (!func->sor.hdmi)
return -ENODEV;
- return disp->sor.hdmi(object, disp, data, size, head, outp);
+ return func->sor.hdmi(object, disp, data, size, head, outp);
case NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT: {
union {
struct nv50_disp_sor_lvds_script_v0 v0;
}
break;
case NV50_DISP_MTHD_V1_PIOR_PWR:
- if (!disp->pior.power)
+ if (!func->pior.power)
return -ENODEV;
- return disp->pior.power(object, disp, data, size, head, outp);
+ return func->pior.power(object, disp, data, size, head, outp);
default:
break;
}
nvkm_wr32(device, 0x610184, tmp);
/* ... CRTC caps */
- for (i = 0; i < disp->head.nr; i++) {
+ for (i = 0; i < disp->base.head.nr; i++) {
tmp = nvkm_rd32(device, 0x616100 + (i * 0x800));
nvkm_wr32(device, 0x610190 + (i * 0x10), tmp);
tmp = nvkm_rd32(device, 0x616104 + (i * 0x800));
}
/* ... DAC caps */
- for (i = 0; i < disp->dac.nr; i++) {
+ for (i = 0; i < disp->func->dac.nr; i++) {
tmp = nvkm_rd32(device, 0x61a000 + (i * 0x800));
nvkm_wr32(device, 0x6101d0 + (i * 0x04), tmp);
}
/* ... SOR caps */
- for (i = 0; i < disp->sor.nr; i++) {
+ for (i = 0; i < disp->func->sor.nr; i++) {
tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800));
nvkm_wr32(device, 0x6101e0 + (i * 0x04), tmp);
}
/* ... PIOR caps */
- for (i = 0; i < disp->pior.nr; i++) {
+ for (i = 0; i < disp->func->pior.nr; i++) {
tmp = nvkm_rd32(device, 0x61e000 + (i * 0x800));
nvkm_wr32(device, 0x6101f0 + (i * 0x04), tmp);
}
projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / commitdiff