x86/intel_rdt: Organize code properly

Having init functions at random places in the middle of the code is
unintuitive.

Move them close to the init routine and mark them __init.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: ravi.v.shankar@intel.com
Cc: tony.luck@intel.com
Cc: fenghua.yu@intel.com
Cc: vikas.shivappa@intel.com

diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index 2802cad0371d4faf5d3f22a97e42c8f0b3537ea0..d2e5f92b5428cd7e0504bde6922be8bc3b10ca3f 100644 (file)
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -168,53 +168,6 @@ static void rdt_get_cdp_l3_config(int type)
        r->enabled = false;
 }
 
-/**
- * Choose a width for the resource name
- * and resource data based on the resource that has
- * widest name and cbm.
- */
-static void rdt_init_padding(void)
-{
-       struct rdt_resource *r;
-       int cl;
-
-       for_each_enabled_rdt_resource(r) {
-               cl = strlen(r->name);
-               if (cl > max_name_width)
-                       max_name_width = cl;
-
-               if (r->data_width > max_data_width)
-                       max_data_width = r->data_width;
-       }
-}
-
-static inline bool get_rdt_resources(void)
-{
-       bool ret = false;
-
-       if (cache_alloc_hsw_probe())
-               return true;
-
-       if (!boot_cpu_has(X86_FEATURE_RDT_A))
-               return false;
-
-       if (boot_cpu_has(X86_FEATURE_CAT_L3)) {
-               rdt_get_config(1, &rdt_resources_all[RDT_RESOURCE_L3]);
-               if (boot_cpu_has(X86_FEATURE_CDP_L3)) {
-                       rdt_get_cdp_l3_config(RDT_RESOURCE_L3DATA);
-                       rdt_get_cdp_l3_config(RDT_RESOURCE_L3CODE);
-               }
-               ret = true;
-       }
-       if (boot_cpu_has(X86_FEATURE_CAT_L2)) {
-               /* CPUID 0x10.2 fields are same format at 0x10.1 */
-               rdt_get_config(2, &rdt_resources_all[RDT_RESOURCE_L2]);
-               ret = true;
-       }
-
-       return ret;
-}
-
 static int get_cache_id(int cpu, int level)
 {
        struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);
@@ -400,6 +353,51 @@ static int intel_rdt_offline_cpu(unsigned int cpu)
        return 0;
 }
 
+/*
+ * Choose a width for the resource name and resource data based on the
+ * resource that has widest name and cbm.
+ */
+static __init void rdt_init_padding(void)
+{
+       struct rdt_resource *r;
+       int cl;
+
+       for_each_enabled_rdt_resource(r) {
+               cl = strlen(r->name);
+               if (cl > max_name_width)
+                       max_name_width = cl;
+
+               if (r->data_width > max_data_width)
+                       max_data_width = r->data_width;
+       }
+}
+
+static __init bool get_rdt_resources(void)
+{
+       bool ret = false;
+
+       if (cache_alloc_hsw_probe())
+               return true;
+
+       if (!boot_cpu_has(X86_FEATURE_RDT_A))
+               return false;
+
+       if (boot_cpu_has(X86_FEATURE_CAT_L3)) {
+               rdt_get_config(1, &rdt_resources_all[RDT_RESOURCE_L3]);
+               if (boot_cpu_has(X86_FEATURE_CDP_L3)) {
+                       rdt_get_cdp_l3_config(RDT_RESOURCE_L3DATA);
+                       rdt_get_cdp_l3_config(RDT_RESOURCE_L3CODE);
+               }
+               ret = true;
+       }
+       if (boot_cpu_has(X86_FEATURE_CAT_L2)) {
+               /* CPUID 0x10.2 fields are same format at 0x10.1 */
+               rdt_get_config(2, &rdt_resources_all[RDT_RESOURCE_L2]);
+               ret = true;
+       }
+       return ret;
+}
+
 static int __init intel_rdt_late_init(void)
 {
        struct rdt_resource *r;