arm64: dts: hip05: fix its node without msi-cells

Fix commit abf9c25d55e8 ("arm64: dts: hip05: Append all gicv3 ITS
entries"), it forgets the property msi-cell, see arm,gic-v3.txt.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index 6319ff3b03ea4d7d411d47a5fecffc4b5a18c80c..52d06ab816dbfd11542fcf41f2a6364bc18fa0a0 100644 (file)
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -249,24 +249,28 @@
                its_peri: interrupt-controller@8c000000 {
                        compatible = "arm,gic-v3-its";
                        msi-controller;
+                       #msi-cells = <1>;
                        reg = <0x0 0x8c000000 0x0 0x40000>;
                };
 
                its_m3: interrupt-controller@a3000000 {
                        compatible = "arm,gic-v3-its";
                        msi-controller;
+                       #msi-cells = <1>;
                        reg = <0x0 0xa3000000 0x0 0x40000>;
                };
 
                its_pcie: interrupt-controller@b7000000 {
                        compatible = "arm,gic-v3-its";
                        msi-controller;
+                       #msi-cells = <1>;
                        reg = <0x0 0xb7000000 0x0 0x40000>;
                };
 
                its_dsa: interrupt-controller@c6000000 {
                        compatible = "arm,gic-v3-its";
                        msi-controller;
+                       #msi-cells = <1>;
                        reg = <0x0 0xc6000000 0x0 0x40000>;
                };
        };