*/
static inline void cls_clear_break(struct channel_t *ch, int force)
{
- ulong lock_flags;
+ unsigned long flags;
if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
return;
- DGNC_LOCK(ch->ch_lock, lock_flags);
+ spin_lock_irqsave(&ch->ch_lock, flags);
/* Bail if we aren't currently sending a break. */
if (!ch->ch_stop_sending_break) {
- DGNC_UNLOCK(ch->ch_lock, lock_flags);
+ spin_unlock_irqrestore(&ch->ch_lock, flags);
return;
}
ch->ch_stop_sending_break = 0;
}
}
- DGNC_UNLOCK(ch->ch_lock, lock_flags);
+ spin_unlock_irqrestore(&ch->ch_lock, flags);
}
{
struct channel_t *ch;
uchar isr = 0;
- ulong lock_flags;
+ unsigned long flags;
/*
* No need to verify board pointer, it was already
/* Transmit Hold register empty pending */
if (isr & UART_IIR_THRI) {
/* Transfer data (if any) from Write Queue -> UART. */
- DGNC_LOCK(ch->ch_lock, lock_flags);
+ spin_lock_irqsave(&ch->ch_lock, flags);
ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
brd->intr_tx++;
ch->ch_intr_tx++;
- DGNC_UNLOCK(ch->ch_lock, lock_flags);
+ spin_unlock_irqrestore(&ch->ch_lock, flags);
cls_copy_data_from_queue_to_uart(ch);
}
{
struct dgnc_board *bd = (struct dgnc_board *) data;
struct channel_t *ch;
- ulong lock_flags;
+ unsigned long flags;
int i;
int state = 0;
int ports = 0;
}
/* Cache a couple board values */
- DGNC_LOCK(bd->bd_lock, lock_flags);
+ spin_lock_irqsave(&bd->bd_lock, flags);
state = bd->state;
ports = bd->nasync;
- DGNC_UNLOCK(bd->bd_lock, lock_flags);
+ spin_unlock_irqrestore(&bd->bd_lock, flags);
/*
* Do NOT allow the interrupt routine to read the intr registers
* Until we release this lock.
*/
- DGNC_LOCK(bd->bd_intr_lock, lock_flags);
+ spin_lock_irqsave(&bd->bd_intr_lock, flags);
/*
* If board is ready, parse deeper to see if there is anything to do.
}
}
- DGNC_UNLOCK(bd->bd_intr_lock, lock_flags);
+ spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
}
struct dgnc_board *brd = (struct dgnc_board *) voidbrd;
uint i = 0;
uchar poll_reg;
- unsigned long lock_flags;
+ unsigned long flags;
if (!brd) {
APR(("Received interrupt (%d) with null board associated\n",
return IRQ_NONE;
}
- DGNC_LOCK(brd->bd_intr_lock, lock_flags);
+ spin_lock_irqsave(&brd->bd_intr_lock, flags);
brd->intr_count++;
/* If 0, no interrupts pending */
if (!poll_reg) {
- DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
+ spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
return IRQ_NONE;
}
*/
tasklet_schedule(&brd->helper_tasklet);
- DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
+ spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
return IRQ_HANDLED;
}
uchar error_mask = 0;
ushort head;
ushort tail;
- ulong lock_flags;
+ unsigned long flags;
if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
return;
- DGNC_LOCK(ch->ch_lock, lock_flags);
+ spin_lock_irqsave(&ch->ch_lock, flags);
/* cache head and tail of queue */
head = ch->ch_r_head;
ch->ch_r_head = head & RQUEUEMASK;
ch->ch_e_head = head & EQUEUEMASK;
- DGNC_UNLOCK(ch->ch_lock, lock_flags);
+ spin_unlock_irqrestore(&ch->ch_lock, flags);
}
*/
static int cls_drain(struct tty_struct *tty, uint seconds)
{
- ulong lock_flags;
+ unsigned long flags;
struct channel_t *ch;
struct un_t *un;
int rc = 0;
if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
return -ENXIO;
- DGNC_LOCK(ch->ch_lock, lock_flags);
+ spin_lock_irqsave(&ch->ch_lock, flags);
un->un_flags |= UN_EMPTY;
- DGNC_UNLOCK(ch->ch_lock, lock_flags);
+ spin_unlock_irqrestore(&ch->ch_lock, flags);
/*
* NOTE: Do something with time passed in.
int n;
int qlen;
uint len_written = 0;
- ulong lock_flags;
+ unsigned long flags;
if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
return;
- DGNC_LOCK(ch->ch_lock, lock_flags);
+ spin_lock_irqsave(&ch->ch_lock, flags);
/* No data to write to the UART */
if (ch->ch_w_tail == ch->ch_w_head) {
- DGNC_UNLOCK(ch->ch_lock, lock_flags);
+ spin_unlock_irqrestore(&ch->ch_lock, flags);
return;
}
/* If port is "stopped", don't send any data to the UART */
if ((ch->ch_flags & CH_FORCED_STOP) ||
(ch->ch_flags & CH_BREAK_SENDING)) {
- DGNC_UNLOCK(ch->ch_lock, lock_flags);
+ spin_unlock_irqrestore(&ch->ch_lock, flags);
return;
}
if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) {
- DGNC_UNLOCK(ch->ch_lock, lock_flags);
+ spin_unlock_irqrestore(&ch->ch_lock, flags);
return;
}
if (len_written > 0)
ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
- DGNC_UNLOCK(ch->ch_lock, lock_flags);
+ spin_unlock_irqrestore(&ch->ch_lock, flags);
}
static void cls_parse_modem(struct channel_t *ch, uchar signals)
{
uchar msignals = signals;
- ulong lock_flags;
+ unsigned long flags;
if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
return;
* Do altpin switching. Altpin switches DCD and DSR.
* This prolly breaks DSRPACE, so we should be more clever here.
*/
- DGNC_LOCK(ch->ch_lock, lock_flags);
+ spin_lock_irqsave(&ch->ch_lock, flags);
if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
uchar mswap = signals;
msignals |= UART_MSR_DCD;
}
}
- DGNC_UNLOCK(ch->ch_lock, lock_flags);
+ spin_unlock_irqrestore(&ch->ch_lock, flags);
/*
* Scrub off lower bits. They signify delta's, which I don't
*/
signals &= 0xf0;
- DGNC_LOCK(ch->ch_lock, lock_flags);
+ spin_lock_irqsave(&ch->ch_lock, flags);
if (msignals & UART_MSR_DCD)
ch->ch_mistat |= UART_MSR_DCD;
else
ch->ch_mistat |= UART_MSR_CTS;
else
ch->ch_mistat &= ~UART_MSR_CTS;
- DGNC_UNLOCK(ch->ch_lock, lock_flags);
+ spin_unlock_irqrestore(&ch->ch_lock, flags);
}