ASoC: nau8825: support different clock source for FLL function
authorJohn Hsu <KCHSU0@nuvoton.com>
Tue, 15 Mar 2016 04:08:21 +0000 (12:08 +0800)
committerMark Brown <broonie@kernel.org>
Mon, 30 May 2016 15:17:44 +0000 (16:17 +0100)
Extend FLL clock source selection. The source can be from MCLK, BCLK or FS.

Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/codecs/nau8825.c
sound/soc/codecs/nau8825.h

index 683769f0f24693bae0ce89eee8938b815721a6fd..b45ca8a320692a9d164524fe42420ebf93ffdb97 100644 (file)
@@ -1069,6 +1069,37 @@ static int nau8825_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
        return 0;
 }
 
+static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
+{
+       int ret = 0;
+
+       nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
+       if (IS_ERR(nau8825->mclk)) {
+               dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
+               return 0;
+       }
+
+       if (!nau8825->mclk_freq) {
+               ret = clk_prepare_enable(nau8825->mclk);
+               if (ret) {
+                       dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
+                       return ret;
+               }
+       }
+
+       if (nau8825->mclk_freq != freq) {
+               freq = clk_round_rate(nau8825->mclk, freq);
+               ret = clk_set_rate(nau8825->mclk, freq);
+               if (ret) {
+                       dev_err(nau8825->dev, "Unable to set mclk rate\n");
+                       return ret;
+               }
+               nau8825->mclk_freq = freq;
+       }
+
+       return 0;
+}
+
 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
        unsigned int freq)
 {
@@ -1080,29 +1111,9 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
                regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
                        NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
                regmap_update_bits(regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
-
-               /* We selected MCLK source but the clock itself managed externally */
-               if (!nau8825->mclk)
-                       break;
-
-               if (!nau8825->mclk_freq) {
-                       ret = clk_prepare_enable(nau8825->mclk);
-                       if (ret) {
-                               dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
-                               return ret;
-                       }
-               }
-
-               if (nau8825->mclk_freq != freq) {
-                       nau8825->mclk_freq = freq;
-
-                       freq = clk_round_rate(nau8825->mclk, freq);
-                       ret = clk_set_rate(nau8825->mclk, freq);
-                       if (ret) {
-                               dev_err(nau8825->dev, "Unable to set mclk rate\n");
-                               return ret;
-                       }
-               }
+               ret = nau8825_mclk_prepare(nau8825, freq);
+               if (ret)
+                       return ret;
 
                break;
        case NAU8825_CLK_INTERNAL:
@@ -1110,7 +1121,32 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
                        NAU8825_DCO_EN);
                regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
                        NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
+               if (nau8825->mclk_freq) {
+                       clk_disable_unprepare(nau8825->mclk);
+                       nau8825->mclk_freq = 0;
+               }
+
+               break;
+       case NAU8825_CLK_FLL_MCLK:
+               regmap_update_bits(regmap, NAU8825_REG_FLL3,
+                       NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_MCLK);
+               ret = nau8825_mclk_prepare(nau8825, freq);
+               if (ret)
+                       return ret;
+
+               break;
+       case NAU8825_CLK_FLL_BLK:
+               regmap_update_bits(regmap, NAU8825_REG_FLL3,
+                       NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_BLK);
+               if (nau8825->mclk_freq) {
+                       clk_disable_unprepare(nau8825->mclk);
+                       nau8825->mclk_freq = 0;
+               }
 
+               break;
+       case NAU8825_CLK_FLL_FS:
+               regmap_update_bits(regmap, NAU8825_REG_FLL3,
+                       NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_FS);
                if (nau8825->mclk_freq) {
                        clk_disable_unprepare(nau8825->mclk);
                        nau8825->mclk_freq = 0;
index 8ceb5f38547846e89239e2023fac8bed20c4359e..ed0d8f3df65f23b84d13bedfc6311a69b6b46239 100644 (file)
 
 /* FLL3 (0x06) */
 #define NAU8825_FLL_INTEGER_MASK               (0x3ff << 0)
+#define NAU8825_FLL_CLK_SRC_SFT                10
+#define NAU8825_FLL_CLK_SRC_MASK               (0x3 << NAU8825_FLL_CLK_SRC_SFT)
+#define NAU8825_FLL_CLK_SRC_MCLK               (0 << NAU8825_FLL_CLK_SRC_SFT)
+#define NAU8825_FLL_CLK_SRC_BLK                (0x2 << NAU8825_FLL_CLK_SRC_SFT)
+#define NAU8825_FLL_CLK_SRC_FS                 (0x3 << NAU8825_FLL_CLK_SRC_SFT)
 
 /* FLL4 (0x07) */
 #define NAU8825_FLL_REF_DIV_MASK               (0x3 << 10)
 enum {
        NAU8825_CLK_MCLK = 0,
        NAU8825_CLK_INTERNAL,
+       NAU8825_CLK_FLL_MCLK,
+       NAU8825_CLK_FLL_BLK,
+       NAU8825_CLK_FLL_FS,
 };
 
 struct nau8825 {