drm/i915: Add csr programming registers to dmc debugfs entry

We check these to determine firmware loading status. Include
them to help to debug causes of firmware loading fails.

v2: Move all CSR specific registers to i915_reg.h (Ville)
v3: Rebase
v4: Rebase (RPM ref)

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446220487-32691-1-git-send-email-mika.kuoppala@intel.com
Tested-by: Daniel Stone <daniels@collabora.com> # SKL
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8096e96c7d3509a94419ca2856012c5e412233ba..e9ecabf791995a60f8eafe0ff10de6063930859b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2802,17 +2802,17 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 
        csr = &dev_priv->csr;
 
+       intel_runtime_pm_get(dev_priv);
+
        seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
        seq_printf(m, "path: %s\n", csr->fw_path);
 
        if (!csr->dmc_payload)
-               return 0;
+               goto out;
 
        seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
                   CSR_VERSION_MINOR(csr->version));
 
-       intel_runtime_pm_get(dev_priv);
-
        if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
                seq_printf(m, "DC3 -> DC5 count: %d\n",
                           I915_READ(SKL_CSR_DC3_DC5_COUNT));
@@ -2823,6 +2823,11 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
                           I915_READ(BXT_CSR_DC3_DC5_COUNT));
        }
 
+out:
+       seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
+       seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
+       seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
+
        intel_runtime_pm_put(dev_priv);
 
        return 0;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 083991271060bd70081a91bb1828e3926aa1ce06..2183a6e1f1343b93102f8b9df129dee33e0e231e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5698,6 +5698,16 @@ enum skl_disp_power_wells {
 #define GAMMA_MODE_MODE_SPLIT  (3 << 0)
 
 /* DMC/CSR */
+#define CSR_PROGRAM(i)         (0x80000 + (i) * 4)
+#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
+#define CSR_HTP_ADDR_SKL       0x00500034
+#define CSR_SSP_BASE           0x8F074
+#define CSR_HTP_SKL            0x8F004
+#define CSR_LAST_WRITE         0x8F034
+#define CSR_LAST_WRITE_VALUE   0xc003b400
+/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
+#define CSR_MMIO_START_RANGE   0x80000
+#define CSR_MMIO_END_RANGE     0x8FFFF
 #define SKL_CSR_DC3_DC5_COUNT  0x80030
 #define SKL_CSR_DC5_DC6_COUNT  0x8002C
 #define BXT_CSR_DC3_DC5_COUNT  0x80038

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 25b6ba723e31554800089dd7d8827f568645f787..7dc53907cd7b346afdfcedde433440897771bdaf 100644 (file)
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -49,21 +49,8 @@ MODULE_FIRMWARE(I915_CSR_BXT);
 
 #define SKL_CSR_VERSION_REQUIRED       CSR_VERSION(1, 23)
 
-/*
-* SKL CSR registers for DC5 and DC6
-*/
-#define CSR_PROGRAM(i)                 (0x80000 + (i) * 4)
-#define CSR_SSP_BASE_ADDR_GEN9         0x00002FC0
-#define CSR_HTP_ADDR_SKL               0x00500034
-#define CSR_SSP_BASE                   0x8F074
-#define CSR_HTP_SKL                    0x8F004
-#define CSR_LAST_WRITE                 0x8F034
-#define CSR_LAST_WRITE_VALUE           0xc003b400
-/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
 #define CSR_MAX_FW_SIZE                        0x2FFF
 #define CSR_DEFAULT_FW_OFFSET          0xFFFFFFFF
-#define CSR_MMIO_START_RANGE   0x80000
-#define CSR_MMIO_END_RANGE             0x8FFFF
 
 struct intel_css_header {
        /* 0x09 for DMC */