[NISTC_G01_STATUS_REG] = { 0x108, 2 },
[NISTC_AI_STATUS2_REG] = { 0, 0 }, /* Unknown */
[NISTC_AO_STATUS2_REG] = { 0x10c, 2 },
- [DIO_Parallel_Input_Register] = { 0, 0 }, /* Unknown */
+ [NISTC_DIO_IN_REG] = { 0, 0 }, /* Unknown */
[G_HW_Save_Register(0)] = { 0x110, 4 },
[G_HW_Save_Register(1)] = { 0x114, 4 },
[G_Save_Register(0)] = { 0x118, 4 },
ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
}
- data[1] = ni_stc_readw(dev, DIO_Parallel_Input_Register);
+ data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
return insn->n;
}
udelay((devpriv->serial_interval_ns + 999) / 2000);
/* Input current bit */
- if (ni_stc_readw(dev, DIO_Parallel_Input_Register) &
- NISTC_DIO_SDIN)
+ if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
input |= mask;
}
#define NISTC_AO_STATUS2_REG 6
-#define DIO_Parallel_Input_Register 7
+#define NISTC_DIO_IN_REG 7
#define AI_SI_Save_Registers 64
#define AI_SC_Save_Registers 66