The pre_pll divisor must be such that ext_clk / pre_pll divisor does not
result in a frequency that is greater than pll_ip_clk_freq. Fix this.
Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
limits->min_pll_ip_freq_hz));
limits->min_pre_pll_clk_div =
max_t(uint16_t, limits->min_pre_pll_clk_div,
- clk_div_even(pll->ext_clk_freq_hz /
- limits->max_pll_ip_freq_hz));
+ clk_div_even_up(
+ DIV_ROUND_UP(pll->ext_clk_freq_hz,
+ limits->max_pll_ip_freq_hz)));
dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %d / %d\n",
limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);