#define DAS16CS_AI_MUX_SINGLE_CHAN(x) (DAS16CS_AI_MUX_HI_CHAN(x) | \
DAS16CS_AI_MUX_LO_CHAN(x))
#define DAS16CS_MISC1_REG 0x04
+#define DAS16CS_MISC1_INTE BIT(15) /* 1=enable; 0=disable */
+#define DAS16CS_MISC1_INT_SRC(x) (((x) & 0x7) << 12) /* interrupt src */
+#define DAS16CS_MISC1_INT_SRC_NONE DAS16CS_MISC1_INT_SRC(0)
+#define DAS16CS_MISC1_INT_SRC_PACER DAS16CS_MISC1_INT_SRC(1)
+#define DAS16CS_MISC1_INT_SRC_EXT DAS16CS_MISC1_INT_SRC(2)
+#define DAS16CS_MISC1_INT_SRC_FNE DAS16CS_MISC1_INT_SRC(3)
+#define DAS16CS_MISC1_INT_SRC_FHF DAS16CS_MISC1_INT_SRC(4)
+#define DAS16CS_MISC1_INT_SRC_EOS DAS16CS_MISC1_INT_SRC(5)
+#define DAS16CS_MISC1_INT_SRC_MASK DAS16CS_MISC1_INT_SRC(7)
+#define DAS16CS_MISC1_OVR BIT(10) /* ro - 1=FIFO overflow */
+#define DAS16CS_MISC1_AI_CONV(x) (((x) & 0x3) << 8) /* AI convert src */
+#define DAS16CS_MISC1_AI_CONV_SW DAS16CS_MISC1_AI_CONV(0)
+#define DAS16CS_MISC1_AI_CONV_EXT_NEG DAS16CS_MISC1_AI_CONV(1)
+#define DAS16CS_MISC1_AI_CONV_EXT_POS DAS16CS_MISC1_AI_CONV(2)
+#define DAS16CS_MISC1_AI_CONV_PACER DAS16CS_MISC1_AI_CONV(3)
+#define DAS16CS_MISC1_AI_CONV_MASK DAS16CS_MISC1_AI_CONV(3)
+#define DAS16CS_MISC1_EOC BIT(7) /* ro - 0=busy; 1=ready */
+#define DAS16CS_MISC1_SEDIFF BIT(5) /* 0=diff; 1=se */
+#define DAS16CS_MISC1_INTB BIT(4) /* ro - 0=latched; 1=cleared */
+#define DAS16CS_MISC1_MA_MASK (0xf << 0) /* ro - current ai mux */
+#define DAS16CS_MISC1_DAC1CS BIT(3) /* wo - DAC1 chip select */
+#define DAS16CS_MISC1_DACCLK BIT(2) /* wo - Serial DAC clock */
+#define DAS16CS_MISC1_DACSD BIT(1) /* wo - Serial DAC data */
+#define DAS16CS_MISC1_DAC0CS BIT(0) /* wo - DAC0 chip select */
+#define DAS16CS_MISC1_DAC_MASK (0x0f << 0)
#define DAS16CS_MISC2_REG 0x06
+#define DAS16CS_MISC2_BME BIT(14) /* 1=burst enable; 0=disable */
+#define DAS16CS_MISC2_AI_GAIN(x) (((x) & 0xf) << 8) /* AI gain */
+#define DAS16CS_MISC2_AI_GAIN_1 DAS16CS_MISC2_AI_GAIN(4) /* +/-10V */
+#define DAS16CS_MISC2_AI_GAIN_2 DAS16CS_MISC2_AI_GAIN(0) /* +/-5V */
+#define DAS16CS_MISC2_AI_GAIN_4 DAS16CS_MISC2_AI_GAIN(1) /* +/-2.5V */
+#define DAS16CS_MISC2_AI_GAIN_8 DAS16CS_MISC2_AI_GAIN(2) /* +-1.25V */
+#define DAS16CS_MISC2_AI_GAIN_MASK DAS16CS_MISC2_AI_GAIN(0xf)
+#define DAS16CS_MISC2_UDIR BIT(7) /* 1=dio7:4 output; 0=input */
+#define DAS16CS_MISC2_LDIR BIT(6) /* 1=dio3:0 output; 0=input */
+#define DAS16CS_MISC2_TRGPOL BIT(5) /* 1=active lo; 0=hi */
+#define DAS16CS_MISC2_TRGSEL BIT(4) /* 1=edge; 0=level */
+#define DAS16CS_MISC2_FFNE BIT(3) /* ro - 1=FIFO not empty */
+#define DAS16CS_MISC2_TRGCLR BIT(3) /* wo - 1=clr (monstable) */
+#define DAS16CS_MISC2_CLK2 BIT(2) /* 1=10 MHz; 0=1 MHz */
+#define DAS16CS_MISC2_CTR1 BIT(1) /* 1=int. 100 kHz; 0=ext. clk */
+#define DAS16CS_MISC2_TRG0 BIT(0) /* 1=enable; 0=disable */
#define DAS16CS_TIMER_BASE 0x08
#define DAS16CS_DIO_REG 0x10
unsigned int status;
status = inw(dev->iobase + DAS16CS_MISC1_REG);
- if (status & 0x0080)
+ if (status & DAS16CS_MISC1_EOC)
return 0;
return -EBUSY;
}
outw(DAS16CS_AI_MUX_SINGLE_CHAN(chan),
dev->iobase + DAS16CS_AI_MUX_REG);
- devpriv->status1 &= ~0xf320;
- devpriv->status1 |= (aref == AREF_DIFF) ? 0 : 0x0020;
+ /* disable interrupts, software convert */
+ devpriv->status1 &= ~(DAS16CS_MISC1_INTE | DAS16CS_MISC1_INT_SRC_MASK |
+ DAS16CS_MISC1_AI_CONV_MASK);
+ if (aref == AREF_DIFF)
+ devpriv->status1 &= ~DAS16CS_MISC1_SEDIFF;
+ else
+ devpriv->status1 |= DAS16CS_MISC1_SEDIFF;
outw(devpriv->status1, dev->iobase + DAS16CS_MISC1_REG);
- devpriv->status2 &= ~0xff00;
+ devpriv->status2 &= ~(DAS16CS_MISC2_BME | DAS16CS_MISC2_AI_GAIN_MASK);
switch (range) {
case 0:
- devpriv->status2 |= 0x800;
+ devpriv->status2 |= DAS16CS_MISC2_AI_GAIN_1;
break;
case 1:
- devpriv->status2 |= 0x000;
+ devpriv->status2 |= DAS16CS_MISC2_AI_GAIN_2;
break;
case 2:
- devpriv->status2 |= 0x100;
+ devpriv->status2 |= DAS16CS_MISC2_AI_GAIN_4;
break;
case 3:
- devpriv->status2 |= 0x200;
+ devpriv->status2 |= DAS16CS_MISC2_AI_GAIN_8;
break;
}
outw(devpriv->status2, dev->iobase + DAS16CS_MISC2_REG);
outw(devpriv->status1, dev->iobase + DAS16CS_MISC1_REG);
udelay(1);
- status1 = devpriv->status1 & ~0xf;
+ /* raise the DACxCS line for the non-selected channel */
+ status1 = devpriv->status1 & ~DAS16CS_MISC1_DAC_MASK;
if (chan)
- status1 |= 0x0001;
+ status1 |= DAS16CS_MISC1_DAC0CS;
else
- status1 |= 0x0008;
+ status1 |= DAS16CS_MISC1_DAC1CS;
outw(status1, dev->iobase + DAS16CS_MISC1_REG);
udelay(1);
for (bit = 15; bit >= 0; bit--) {
- int b = (val >> bit) & 0x1;
-
- b <<= 1;
- outw(status1 | b | 0x0000,
- dev->iobase + DAS16CS_MISC1_REG);
+ if ((val >> bit) & 0x1)
+ status1 |= DAS16CS_MISC1_DACSD;
+ else
+ status1 &= ~DAS16CS_MISC1_DACSD;
+ outw(status1, dev->iobase + DAS16CS_MISC1_REG);
udelay(1);
- outw(status1 | b | 0x0004,
+ outw(status1 | DAS16CS_MISC1_DACCLK,
dev->iobase + DAS16CS_MISC1_REG);
udelay(1);
}
* Make both DAC0CS and DAC1CS high to load
* the new data and update analog the output
*/
- outw(status1 | 0x9, dev->iobase + DAS16CS_MISC1_REG);
+ outw(status1 | DAS16CS_MISC1_DAC0CS | DAS16CS_MISC1_DAC1CS,
+ dev->iobase + DAS16CS_MISC1_REG);
}
s->readback[chan] = val;
if (ret)
return ret;
- devpriv->status2 &= ~0x00c0;
- devpriv->status2 |= (s->io_bits & 0xf0) ? 0x0080 : 0;
- devpriv->status2 |= (s->io_bits & 0x0f) ? 0x0040 : 0;
-
+ if (s->io_bits & 0xf0)
+ devpriv->status2 |= DAS16CS_MISC2_UDIR;
+ else
+ devpriv->status2 &= ~DAS16CS_MISC2_UDIR;
+ if (s->io_bits & 0x0f)
+ devpriv->status2 |= DAS16CS_MISC2_LDIR;
+ else
+ devpriv->status2 &= ~DAS16CS_MISC2_LDIR;
outw(devpriv->status2, dev->iobase + DAS16CS_MISC2_REG);
return insn->n;