[9610] arm64: dsti: added fimc_is configuration

Change-Id: I48440e0edf04e2fc3fd523a77088527ea1808a28
Signed-off-by: Eunyoung Lee <ey470.lee@samsung.com>

diff --git a/arch/arm64/boot/dts/exynos/exynos9610-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos9610-pinctrl.dtsi
index 26743ebb2975b98991d803ba2fbfc5734831715f..17a61440f60226018179ccc50af74a80cfe34906 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos9610-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos9610-pinctrl.dtsi
@@ -1148,6 +1148,69 @@
                        samsung,pin-drv = <0>;
                };
 
+               fimc_is_mclk0_in: fimc_is_mclk0_in {
+                       samsung,pins = "gpc2-0";
+                       samsung,pin-function = <0>;
+                       samsung,pin-pud = <0>;
+                       samsung,pin-drv = <2>;
+               };
+
+               fimc_is_mclk1_in: fimc_is_mclk1_in {
+                       samsung,pins = "gpc2-1";
+                       samsung,pin-function = <0>;
+                       samsung,pin-pud = <0>;
+                       samsung,pin-drv = <2>;
+               };
+
+               fimc_is_mclk2_in: fimc_is_mclk2_in {
+                       samsung,pins = "gpc2-2";
+                       samsung,pin-function = <0>;
+                       samsung,pin-pud = <0>;
+                       samsung,pin-drv = <2>;
+               };
+
+               fimc_is_mclk0_out: fimc_is_mclk0_out {
+                       samsung,pins = "gpc2-0";
+                       samsung,pin-function = <1>;
+                       samsung,pin-pud = <1>;
+                       samsung,pin-drv = <2>;
+               };
+
+               fimc_is_mclk1_out: fimc_is_mclk1_out {
+                       samsung,pins = "gpc2-1";
+                       samsung,pin-function = <1>;
+                       samsung,pin-pud = <1>;
+                       samsung,pin-drv = <2>;
+               };
+
+               fimc_is_mclk2_out: fimc_is_mclk2_out {
+                       samsung,pins = "gpc2-2";
+                       samsung,pin-function = <1>;
+                       samsung,pin-pud = <1>;
+                       samsung,pin-drv = <2>;
+               };
+
+               fimc_is_mclk0_fn: fimc_is_mclk0_fn {
+                       samsung,pins = "gpc2-0";
+                       samsung,pin-function = <2>;
+                       samsung,pin-pud = <0>;
+                       samsung,pin-drv = <2>;
+               };
+
+               fimc_is_mclk1_fn: fimc_is_mclk1_fn {
+                       samsung,pins = "gpc2-1";
+                       samsung,pin-function = <2>;
+                       samsung,pin-pud = <0>;
+                       samsung,pin-drv = <2>;
+               };
+
+               fimc_is_mclk2_fn: fimc_is_mclk2_fn {
+                       samsung,pins = "gpc2-2";
+                       samsung,pin-function = <2>;
+                       samsung,pin-pud = <0>;
+                       samsung,pin-drv = <2>;
+               };
+
                decon_f_te_on: decon_f_te_on {
                        samsung,pins = "gpc2-3";
                        samsung,pin-function = <0xf>;

diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/dts/exynos/exynos9610.dtsi
index 543f9ecec4b6183865cac5eb385f91134eb57490..bd5b26841255207d345984013e3a4bc57a05c9cd 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi
@@ -24,6 +24,7 @@
 #include "exynos9610-pm-domains.dtsi"
 #include <dt-bindings/soc/samsung/exynos9610-devfreq.h>
 #include "exynos9610-mfc.dtsi"
+#include <dt-bindings/camera/fimc_is.h>
 
 / {
        compatible = "samsung,armv8", "samsung,exynos9610";
@@ -1846,9 +1847,6 @@
                #include "exynos9610-tmu-sensor-conf.dtsi"
        };
 
-       fimc_is: dummy@1A000000 {
-       };
-
        acpm_tmu {
                acpm-ipc-channel = <7>;
        };
@@ -2945,7 +2943,8 @@
                #size-cells = <1>;
                ranges;
 
-               domain-clients = <>;
+               domain-clients = <&fimc_is>, <&fimc_is_sensor0>, <&fimc_is_sensor1>,
+                       <&fimc_is_sensor2>, <&fimc_is_sensor3>, <&camerapp_gdc>;
        };
 
        iommu-domain_mfc {
@@ -3156,6 +3155,7 @@
                compatible = "samsung,exynos-tee";
                interrupts = <0 454 0>;
        };
+
        baaw_p_wlbt: syscon@12050000 {
                compatible = "baaw_p_wlbt", "syscon";
                reg = <0x0 0x12050000 0xff>;
@@ -3307,4 +3307,392 @@
                samsung,power-domain = <&pd_dispaud>;
                status = "disabled";
        };
+
+       fimc_is: fimc_is@144B0000 {
+               compatible = "samsung,exynos5-fimc-is";
+               #pb-id-cells = <6>;
+               reg = <0x0 0x14490000 0x100>, /* CSIS COMMON DMA */
+                       <0x0 0x144B0000 0x10000>, /* FIMC-3AA0 */
+                       <0x0 0x144B0000 0x10000>, /* FIMC-3AA1 */
+                       <0x0 0x14600000 0x10000>, /* FIMC_ISP */
+                       <0x0 0x14640000 0x10000>, /* MC_SCALER */
+                       <0x0 0x14610000 0x10000>, /* FIMC-VRA (Set A) */
+                       <0x0 0x14620000 0x10000>, /* FIMC-VRA (Set B) */
+                       <0x0 0x144A0000 0x100>; /* PAFSTAT RDMA */
+               interrupts = <0 335 0>, /* 3AA0_0 */
+                       <0 336 0>, /* 3AA0_1 */
+                       <0 337 0>, /* 3AA1_0 */
+                       <0 338 0>, /* 3AA1_1 */
+                       <0 344 0>, /* ISP_0 */
+                       <0 345 0>, /* ISP_1 */
+                       <0 348 0>, /* MC_SC_0 */
+                       <0 346 0>; /* VRA_1 */
+               pinctrl-names = "default","release";
+               pinctrl-0 = <>;
+               pinctrl-1 = <>;
+               samsung,power-domain = <&pd_isp>;
+               clocks = <&clock UMUX_CLKCMU_CAM_BUS>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_3AA>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_RDMA>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_SMMU>,
+
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS0>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS1>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS2>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS3>,
+                       <&clock CIS_CLK0>,
+                       <&clock CIS_CLK1>,
+                       <&clock CIS_CLK2>,
+                       <&clock CIS_CLK3>,
+
+                       <&clock UMUX_CLKCMU_ISP_BUS>,
+                       <&clock UMUX_CLKCMU_ISP_GDC>,
+                       <&clock UMUX_CLKCMU_ISP_VRA>,
+                       <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_ISP>,
+                       <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_MCSC>,
+                       <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_VRA>,
+                       <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_GDC>,
+                       <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0>,
+                       <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1>;
+               clock-names = "UMUX_CLKCMU_CAM_BUS",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_3AA",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_CORE",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_PDP_DMA",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_RDMA",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_SMMU",
+
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS0",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS1",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS2",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS3",
+                       "CIS_CLK0",
+                       "CIS_CLK1",
+                       "CIS_CLK2",
+                       "CIS_CLK3",
+
+                       "UMUX_CLKCMU_ISP_BUS",
+                       "UMUX_CLKCMU_ISP_GDC",
+                       "UMUX_CLKCMU_ISP_VRA",
+                       "GATE_IS6P10P0_ISP_QCH_S_ISP_ISP",
+                       "GATE_IS6P10P0_ISP_QCH_S_ISP_MCSC",
+                       "GATE_IS6P10P0_ISP_QCH_S_ISP_VRA",
+                       "GATE_IS6P10P0_ISP_QCH_S_ISP_GDC",
+                       "GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP0",
+                       "GATE_IS6P10P0_ISP_QCH_S_ISP_SMMU_ISP1";
+               status = "ok";
+               iommus = <&sysmmu_isp0>, <&sysmmu_isp1>, <&sysmmu_cam>;
+               #cooling-cells = <2>; /* min followed by max */
+       };
+
+       mipi_phy_csis_m4s4s4: dphy_m4s4s4_csis@0x14510800 {
+               /* DCPHY 4.5 Gbps 4lane */
+               compatible = "samsung,mipi-phy-m4s4-top";
+               samsung,pmu-syscon = <&pmu_system_controller>;
+               isolation = <0x70C 0x70C>; /* PMU address offset */
+               reg = <0x0 0x14510800 0x4>; /* SYSREG address for reset */
+               reset = <4 8>; /* reset bit */
+               owner = <1>; /* 0: DSI,  1: CSI */
+               #phy-cells = <1>;
+       };
+
+       mipi_phy_csis_m2s4s4s2: dphy_m2s4s4s2_csis@0x14510800 {
+               /* DPHY 2.5 Gbps 4lane */
+               compatible = "samsung,mipi-phy-m4s4-mod";
+               samsung,pmu-syscon = <&pmu_system_controller>;
+               isolation = <0x710 0x710 0x710>; /* PMU address offset */
+               reset = <12 16 0>; /* reset bit */
+               owner = <1>; /* 0: DSI,  1: CSI */
+               #phy-cells = <1>;
+       };
+
+       fimc_is_sensor0: fimc_is_sensor@14400000 {
+               /* REAR/CSIS0 */
+               compatible = "samsung,exynos5-fimc-is-sensor";
+               #pb-id-cells = <4>;
+               reg = <0x0 0x14400000 0x700>, /* MIPI-CSI0 */
+                       <0x0 0x14400700 0x100>, /* PHY: TOP_M4S4S4 */
+
+                       <0x0 0x14450000 0x100>, /* VC0 DMA0 */
+                       <0x0 0x14450400 0x100>, /* VC0 DMA0 COMMON */
+                       <0x0 0x14450100 0x100>, /* VC1 DMA0 */
+                       <0x0 0x14450400 0x100>, /* VC1 DMA0 COMMON */
+                       <0x0 0x14450200 0x100>, /* VC2 DMA0 */
+                       <0x0 0x14450400 0x100>, /* VC2 DMA0 COMMON */
+                       <0x0 0x14450300 0x100>, /* VC3 DMA0 */
+                       <0x0 0x14450400 0x100>, /* VC3 DMA0 COMMON */
+
+                       <0x0 0x14450000 0x100>, /* VC0 DMA0 */
+                       <0x0 0x14450400 0x100>, /* VC0 DMA0 COMMON */
+                       <0x0 0x14460100 0x100>, /* VC1 DMA1 */
+                       <0x0 0x14460400 0x100>, /* VC1 DMA1 COMMON */
+                       <0x0 0x14460200 0x100>, /* VC2 DMA1 */
+                       <0x0 0x14460400 0x100>, /* VC2 DMA1 COMMON */
+                       <0x0 0x14460300 0x100>, /* VC3 DMA1 */
+                       <0x0 0x14460400 0x100>; /* VC3 DMA1 COMMON */
+               interrupts = <0 325 0>, /* MIPI-CSI0 */
+                       <0 331 0>, /* VC0 DMA0 */
+                       <0 331 0>, /* VC1 DMA0 */
+                       <0 331 0>, /* VC2 DMA0 */
+                       <0 331 0>, /* VC3 DMA0 */
+
+                       <0 331 0>, /* VC0 DMA0 */
+                       <0 332 0>, /* VC1 DMA1 */
+                       <0 332 0>, /* VC2 DMA1 */
+                       <0 332 0>; /* VC3 DMA1 */
+               samsung,power-domain = <&pd_cam>;
+               phys = <&mipi_phy_csis_m4s4s4 0>;
+               phy-names = "csis_dphy";
+               clocks = <&clock CIS_CLK0>,
+                       <&clock CIS_CLK1>,
+                       <&clock CIS_CLK2>,
+                       <&clock CIS_CLK3>,
+
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS0>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS1>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS2>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS3>,
+
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3>;
+               clock-names = "CIS_CLK0",
+                       "CIS_CLK1",
+                       "CIS_CLK2",
+                       "CIS_CLK3",
+
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS0",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS1",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS2",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS3",
+
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3";
+               iommus = <&sysmmu_cam>;
+       };
+
+       fimc_is_sensor1: fimc_is_sensor@14410000 {
+               /* FRONT/CSIS1 */
+               compatible = "samsung,exynos5-fimc-is-sensor";
+               #pb-id-cells = <4>;
+               reg = <0x0 0x14410000 0x700>, /* MIPI-CSI0 */
+                       <0x0 0x14410700 0x100>, /* PHY: TOP_M2S4S4S2 */
+
+                       <0x0 0x14460000 0x100>, /* VC0 DMA1 */
+                       <0x0 0x14460400 0x100>, /* VC0 DMA1 COMMON */
+                       <0x0 0x14460100 0x100>, /* VC1 DMA1 */
+                       <0x0 0x14460400 0x100>, /* VC1 DMA1 COMMON */
+                       <0x0 0x14460200 0x100>, /* VC2 DMA1 */
+                       <0x0 0x14460400 0x100>, /* VC2 DMA1 COMMON */
+                       <0x0 0x14460300 0x100>, /* VC3 DMA1 */
+                       <0x0 0x14460400 0x100>, /* VC3 DMA1 COMMON */
+
+                       <0x0 0x14460000 0x100>, /* VC1 DMA1 */
+                       <0x0 0x14460400 0x100>, /* VC1 DMA1 COMMON */
+                       <0x0 0x14460100 0x100>, /* VC2 DMA1 */
+                       <0x0 0x14460400 0x100>, /* VC2 DMA1 COMMON */
+                       <0x0 0x14460200 0x100>, /* VC1 DMA1 */
+                       <0x0 0x14460400 0x100>, /* VC1 DMA1 COMMON */
+                       <0x0 0x14460300 0x100>, /* VC3 DMA1 */
+                       <0x0 0x14460400 0x100>; /* VC3 DMA1 COMMON */
+               interrupts = <0 326 0>, /* MIPI-CSI1 */
+                       <0 332 0>, /* VC0 DMA1 */
+                       <0 332 0>, /* VC1 DMA1 */
+                       <0 332 0>, /* VC2 DMA1 */
+                       <0 332 0>, /* VC3 DMA1 */
+
+                       <0 332 0>, /* VC1 DMA2 */
+                       <0 332 0>, /* VC2 DMA1 */
+                       <0 332 0>, /* VC1 DMA1 */
+                       <0 332 0>; /* VC3 DMA1 */
+               samsung,power-domain = <&pd_cam>;
+               phys = <&mipi_phy_csis_m2s4s4s2 0>;
+               phy-names = "csis_dphy";
+               clocks = <&clock CIS_CLK0>,
+                       <&clock CIS_CLK1>,
+                       <&clock CIS_CLK2>,
+                       <&clock CIS_CLK3>,
+
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS0>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS1>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS2>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS3>,
+
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3>;
+               clock-names = "CIS_CLK0",
+                       "CIS_CLK1",
+                       "CIS_CLK2",
+                       "CIS_CLK3",
+
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS0",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS1",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS2",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS3",
+
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3";
+               iommus = <&sysmmu_cam>;
+       };
+
+       fimc_is_sensor2: fimc_is_sensor@14420000 {
+               /* REAR2/CSIS2 */
+               compatible = "samsung,exynos5-fimc-is-sensor";
+               #pb-id-cells = <4>;
+               reg = <0x0 0x14420000 0x700>, /* MIPI-CSI0 */
+                       <0x0 0x14420700 0x100>, /* PHY: TOP_M4S4S4_2nd */
+
+                       <0x0 0x14470000 0x100>, /* VC0 DMA2 */
+                       <0x0 0x14470400 0x100>, /* VC0 DMA2 COMMON */
+                       <0x0 0x14470100 0x100>, /* VC1 DMA2 */
+                       <0x0 0x14470400 0x100>, /* VC1 DMA2 COMMON */
+                       <0x0 0x14470200 0x100>, /* VC2 DMA2 */
+                       <0x0 0x14470400 0x100>, /* VC2 DMA2 COMMON */
+                       <0x0 0x14470300 0x100>, /* VC3 DMA2 */
+                       <0x0 0x14470400 0x100>; /* VC3 DMA2 COMMON */
+               interrupts = <0 327 0>, /* MIPI-CSI2 */
+                       <0 333 0>, /* VC0 DMA2 */
+                       <0 333 0>, /* VC1 DMA2 */
+                       <0 333 0>, /* VC2 DMA2 */
+                       <0 333 0>; /* VC3 DMA2 */
+               samsung,power-domain = <&pd_cam>;
+               phys = <&mipi_phy_csis_m4s4s4 1>;
+               phy-names = "csis_dphy";
+               clocks = <&clock CIS_CLK0>,
+                       <&clock CIS_CLK1>,
+                       <&clock CIS_CLK2>,
+                       <&clock CIS_CLK3>,
+
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS0>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS1>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS2>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS3>,
+
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3>;
+               clock-names = "CIS_CLK0",
+                       "CIS_CLK1",
+                       "CIS_CLK2",
+                       "CIS_CLK3",
+
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS0",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS1",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS2",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS3",
+
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3";
+               iommus = <&sysmmu_cam>;
+       };
+
+       fimc_is_sensor3: fimc_is_sensor@14430000 {
+               /* IRIS/CSIS3 */
+               compatible = "samsung,exynos5-fimc-is-sensor";
+               #pb-id-cells = <4>;
+               reg = <0x0 0x14430000 0x0700>, /* MIPI-CSI0 */
+                       <0x0 0x14430700 0x100>, /* PHY: TOP_M2S4S4S2 */
+
+                       <0x0 0x14480000 0x100>, /* VC0 DMA3 */
+                       <0x0 0x14480400 0x100>, /* VC0 DMA3 COMMON */
+                       <0x0 0x14480100 0x100>, /* VC1 DMA3 */
+                       <0x0 0x14480400 0x100>, /* VC1 DMA3 COMMON */
+                       <0x0 0x14480200 0x100>, /* VC2 DMA3 */
+                       <0x0 0x14480400 0x100>, /* VC2 DMA3 COMMON */
+                       <0x0 0x14480300 0x100>, /* VC3 DMA3 */
+                       <0x0 0x14480400 0x100>; /* VC3 DMA3 COMMON */
+               interrupts = <0 328 0>, /* MIPI-CSI3 */
+                       <0 334 0>, /* VC0 DMA3 */
+                       <0 334 0>, /* VC1 DMA3 */
+                       <0 334 0>, /* VC2 DMA3 */
+                       <0 334 0>; /* VC3 DMA3 */
+               samsung,power-domain = <&pd_cam>;
+               phys = <&mipi_phy_csis_m2s4s4s2 2>;
+               phy-names = "csis_dphy";
+               clocks = <&clock CIS_CLK0>,
+                       <&clock CIS_CLK1>,
+                       <&clock CIS_CLK2>,
+                       <&clock CIS_CLK3>,
+
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS0>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS1>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS2>,
+                       <&clock GATE_DFTMUX_TOP_QCH_CLK_CSIS3>,
+
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2>,
+                       <&clock GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3>;
+               clock-names = "CIS_CLK0",
+                       "CIS_CLK1",
+                       "CIS_CLK2",
+                       "CIS_CLK3",
+
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS0",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS1",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS2",
+                       "GATE_DFTMUX_TOP_QCH_CLK_CSIS3",
+
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS0",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS1",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS2",
+                       "GATE_IS6P10P0_CAM_QCH_S_CAM_CSIS3";
+               iommus = <&sysmmu_cam>;
+       };
+
+       fimc_is_pafstat0: fimc_is_pafstat@14440000 {
+               /* PAFSTAT CORE0 */
+               compatible = "samsung,exynos5-fimc-is-pafstat";
+               reg = <0x0 0x14440000 0x1000>,
+                       <0x0 0x14448000 0x1000>; /* PAFSTAT CONTEXT0 */
+               interrupts = <0 329 0>;
+               id = <0>;
+       };
+
+       fimc_is_pafstat1: fimc_is_pafstat@14444000 {
+               /* PDP CORE1 */
+               compatible = "samsung,exynos5-fimc-is-pafstat";
+               reg = <0x0 0x14444000 0x1000>,
+                       <0x0 0x1444C000 0x1000>; /* PAFSTAT CONTEXT1 */
+               interrupts = <0 330 0>;
+               id = <1>;
+       };
+
+       camerapp_gdc: gdc@14630000 {
+               compatible = "samsung,exynos5-camerapp-gdc";
+               #pb-id-cells = <6>;
+               reg = <0x0 0x14630000 0x10000>; /* GDC */
+               interrupts = <0 347 0>; /* GDC */
+               pinctrl-names = "default","release";
+               pinctrl-0 = <>;
+               pinctrl-1 = <>;
+               camerapp_gdc,intcam_qos_minlock = <667000>;
+               samsung,power-domain = <&pd_isp>;
+               clocks = <&clock UMUX_CLKCMU_ISP_GDC>,
+                       <&clock GATE_IS6P10P0_ISP_QCH_S_ISP_GDC>;
+               clock-names = "gate",
+                       "gate2";
+               status = "ok";
+               iommus = <&sysmmu_isp0>;
+               #cooling-cells = <2>; /* min followed by max */
+       };
 };