mtd: nand: gpmi: reset BCH earlier, too, to avoid NAND startup problems

It could happen (1 out of 100 times) that NAND did not start up
correctly after warm rebooting, so the kernel could not find the UBI or
DMA timed out due to a stalled BCH. When resetting BCH together with
GPMI, the issue could not be observed anymore (after 10000+ reboots). We
probably need the consistent state already before sending any command to
NAND, even when no ECC is needed. I chose to keep the extra reset for
BCH when changing the flash layout to be on the safe side.

Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Huang Shijie <b32955@freescale.com>
Cc: stable@vger.kernel.org
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 1585c5b1c8bf733428fda151e603c8a489d92605..d84699c7968e4e854d394c94f07ec4b8fdd4fcf6 100644 (file)
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -165,6 +165,15 @@ int gpmi_init(struct gpmi_nand_data *this)
        if (ret)
                goto err_out;
 
+       /*
+        * Reset BCH here, too. We got failures otherwise :(
+        * See later BCH reset for explanation of MX23 handling
+        */
+       ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
+       if (ret)
+               goto err_out;
+
+
        /* Choose NAND mode. */
        writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR);