ARM: imx: add gpt_3m clk for i.mx6qdl
authorAnson Huang <b20788@freescale.com>
Thu, 11 Sep 2014 03:29:40 +0000 (11:29 +0800)
committerShawn Guo <shawn.guo@freescale.com>
Tue, 16 Sep 2014 02:09:40 +0000 (10:09 +0800)
Add gpt_3m clock for i.mx6qdl, as gpt can source clock
from OSC, some i.MX6 series SOCs has fixed divider of
8 for gpt clock, so here add a fix clk of gpt_3m.

i.MX6Q TO1.0 has no gpt_3m option, so force it to be
from ipg_per.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
arch/arm/mach-imx/clk-imx6q.c
include/dt-bindings/clock/imx6qdl-clock.h

index 4f8ce60a2e90d15afc7c9718cd0c8f179d092265..1412daf4a7145c2464420faabad509a1d11dc4ae 100644 (file)
@@ -245,6 +245,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        clk[IMX6QDL_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
        clk[IMX6QDL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
        clk[IMX6QDL_CLK_TWD]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
+       clk[IMX6QDL_CLK_GPT_3M]    = imx_clk_fixed_factor("gpt_3m",    "osc",            1, 8);
        if (cpu_is_imx6dl()) {
                clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
                clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
@@ -461,6 +462,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        clk[IMX6QDL_CLK_CKO1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
        clk[IMX6QDL_CLK_CKO2]         = imx_clk_gate("cko2",           "cko2_podf",         base + 0x60, 24);
 
+       /*
+        * The gpt_3m clock is not available on i.MX6Q TO1.0.  Let's point it
+        * to clock gpt_ipg_per to ease the gpt driver code.
+        */
+       if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
+               clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER];
+
        imx_check_clocks(clk, ARRAY_SIZE(clk));
 
        clk_data.clks = clk;
index c0d88ab013b45d95a9c2d63e77e633be4557bda3..ddaef8620b2c2b72bbceb19e1068e302b8711ff4 100644 (file)
 #define IMX6QDL_PLL5_BYPASS                    234
 #define IMX6QDL_PLL6_BYPASS                    235
 #define IMX6QDL_PLL7_BYPASS                    236
-#define IMX6QDL_CLK_END                                237
+#define IMX6QDL_CLK_GPT_3M                     237
+#define IMX6QDL_CLK_END                                238
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */