drm/i915/gen9: Add WaOCLCoherentLineFlush

This is mainly required for future enabling of pre-emptive
command execution.

v2: explain purpose of change (Chris)

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-9-git-send-email-arun.siluvery@linux.intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d07c6a9e7b40c1127be00baa15daa4167119e7f3..6f5b511bdb5d9b41eea7011f477e9bbcf663030b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -981,6 +981,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
        /* WaDisableSTUnitPowerOptimization:skl,bxt */
        WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 
+       /* WaOCLCoherentLineFlush:skl,bxt */
+       I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+                                   GEN8_LQSC_FLUSH_COHERENT_LINES));
+
        /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
        ret= wa_ring_whitelist_reg(ring, GEN8_CS_CHICKEN1);
        if (ret)