powerpc/mpc5200: PCI write combine timer

On MPC5200 the PCI target control register (PCITCR) @ MBAR + 0xD6C is
initialized with only bit 7 (Latrule disable) set. The 8-Bit write
combine timer (Bits 24..31) should be also set to a reasonable value
_greater zero_ (0x08 = default) since setting it to 0x00 leads to
_very poor_ performance as a PCI target since external burst won't be
possible at all.

Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pci.c b/arch/powerpc/platforms/52xx/mpc52xx_pci.c
index e3428ddd9040df88e77380775a0f9cc688fb7824..5a382bb15f6266a8c8835c9e8eef4d2951dc84ae 100644 (file)
--- a/arch/powerpc/platforms/52xx/mpc52xx_pci.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pci.c
@@ -63,6 +63,7 @@
 
 #define MPC52xx_PCI_TCR_P              0x01000000
 #define MPC52xx_PCI_TCR_LD             0x00010000
+#define MPC52xx_PCI_TCR_WCT8           0x00000008
 
 #define MPC52xx_PCI_TBATR_DISABLE      0x0
 #define MPC52xx_PCI_TBATR_ENABLE       0x1
@@ -313,7 +314,7 @@ mpc52xx_pci_setup(struct pci_controller *hose,
        out_be32(&pci_regs->tbatr1,
                MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_MEM );
 
-       out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD);
+       out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD | MPC52xx_PCI_TCR_WCT8);
 
        tmp = in_be32(&pci_regs->gscr);
 #if 0