drm/nouveau/disp/dp: support training pattern 3

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
index 46563da2854e8d27715ee001051e279971df6cd4..13903533d7a246c3a8aab8ce5c95cf47ddf1d70e 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
@@ -202,7 +202,10 @@ dp_link_train_eq(struct dp_state *dp)
        bool eq_done = false, cr_done = true;
        int tries = 0, i;
 
-       dp_set_training_pattern(dp, 2);
+       if (dp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED)
+               dp_set_training_pattern(dp, 3);
+       else
+               dp_set_training_pattern(dp, 2);
 
        do {
                if (dp_link_train_update(dp, 400))
@@ -316,8 +319,10 @@ nouveau_dp_train(struct nouveau_disp *disp, const struct nouveau_dp_func *func,
        }
 
        /* bring capabilities within encoder limits */
+       if (nv_oclass(disp)->handle < NV_ENGINE(DISP, 0x90))
+               dp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED;
        if ((dp->dpcd[2] & 0x1f) > dp->outp->dpconf.link_nr) {
-               dp->dpcd[2] &= ~0x1f;
+               dp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT;
                dp->dpcd[2] |= dp->outp->dpconf.link_nr;
        }
        if (dp->dpcd[1] > dp->outp->dpconf.link_bw)

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.h b/drivers/gpu/drm/nouveau/core/engine/disp/dport.h
index 4d375b759baf3b948ceb430c4594934fc3b19a47..43281c8e9e7b0f323a0148cc51d2335d05ee5ed4 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.h
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dport.h
@@ -6,6 +6,7 @@
 #define DPCD_RC01_MAX_LINK_RATE                                         0x00001
 #define DPCD_RC02                                                       0x00002
 #define DPCD_RC02_ENHANCED_FRAME_CAP                                       0x80
+#define DPCD_RC02_TPS3_SUPPORTED                                           0x40
 #define DPCD_RC02_MAX_LANE_COUNT                                           0x1f
 #define DPCD_RC03                                                       0x00003
 #define DPCD_RC03_MAX_DOWNSPREAD                                           0x01