if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
canvas_align_width = 64;
- pr_info("%s:begin\n", __func__);
+ dbg_reg("%s:begin\n", __func__);
frame_count = 0;
disp_frame_count = 0;
cur_post_ready_di_buf = NULL;
di_lock_irqfiq_save(irq_flag2); /**/
di_que_out(channel, QUE_POST_BACK, di_buf);
di_buf->queue_index = QUEUE_DISPLAY;
- queue_out(channel, di_buf);
+ /*queue_out(channel, di_buf);*/
if (!atomic_dec_and_test(&di_buf->di_cnt))
PR_ERR("%s,di_cnt > 0\n", __func__);
- /*recycle_vframe_type_post(di_buf, channel);*/
- di_buf->invert_top_bot_flag = 0;
- di_que_in(channel, QUE_POST_FREE, di_buf);
+ recycle_vframe_type_post(di_buf, channel);
+ //di_buf->invert_top_bot_flag = 0;
+ //di_que_in(channel, QUE_POST_FREE, di_buf);
di_unlock_irqfiq_restore(irq_flag2);
}
}
/**************************/
dim_log_buffer_state("pek", channel);
- task_send_ready();
+
#ifdef SUPPORT_START_FRAME_HOLD
if ((disp_frame_count == 0) && (dim_is_bypass(NULL, channel) == 0)) {
int ready_count = di_que_list_count(channel, QUE_POST_READY);
#endif
if (vframe_ret)
dim_tr_ops.post_peek(9);
- else
+ else {
+ task_send_ready();
dim_tr_ops.post_peek(4);
+ }
return vframe_ret;
}
/*new use this for put back control*/
#define QUEUE_POST_PUT_BACK (9)
+#define QUEUE_POST_KEEP (10)/*below use pw_queue_in*/
+#define QUEUE_POST_KEEP_BACK (11)
#define QUEUE_NUM 5 /* 9 */
#define QUEUE_NEW_THD_MIN (QUEUE_IN_FREE - 1)
-#define QUEUE_NEW_THD_MAX (QUEUE_POST_READY + 1)
+#define QUEUE_NEW_THD_MAX (QUEUE_POST_KEEP_BACK + 1)
#endif
ext_ops.switch_vpu_mem_pd_vmod(VPU_DI_POST,
false);
}
- pr_info("%s:%d\n", __func__, on);
+ /*pr_info("%s:%d\n", __func__, on);*/
}
void hpst_dbg_power_ctr_trig(unsigned int cmd)
#define COM_MV(a, m, v) (((a) & (m)) == (v))
#define COM_ME(a, m) (((a) & (m)) == (m))
-#define DI_BIT0 0x01
-#define DI_BIT1 0x02
-#define DI_BIT2 0x04
-#define DI_BIT3 0x08
+#define DI_BIT0 0x00000001
+#define DI_BIT1 0x00000002
+#define DI_BIT2 0x00000004
+#define DI_BIT3 0x00000008
+#define DI_BIT4 0x00000010
+#define DI_BIT5 0x00000020
+#define DI_BIT6 0x00000040
+#define DI_BIT7 0x00000080
+#define DI_BIT8 0x00000100
+#define DI_BIT9 0x00000200
+#define DI_BIT10 0x00000400
+#define DI_BIT11 0x00000800
+#define DI_BIT12 0x00001000
+#define DI_BIT13 0x00002000
+#define DI_BIT14 0x00004000
+#define DI_BIT15 0x00008000
+#define DI_BIT16 0x00010000
+#define DI_BIT17 0x00020000
+#define DI_BIT18 0x00040000
+#define DI_BIT19 0x00080000
+#define DI_BIT20 0x00100000
+#define DI_BIT21 0x00200000
+#define DI_BIT22 0x00400000
+#define DI_BIT23 0x00800000
+#define DI_BIT24 0x01000000
+#define DI_BIT25 0x02000000
+#define DI_BIT26 0x04000000
+#define DI_BIT27 0x08000000
+#define DI_BIT28 0x10000000
+#define DI_BIT29 0x20000000
+#define DI_BIT30 0x40000000
+#define DI_BIT31 0x80000000
/*****************************************
*
#define DBG_M_POLLING 0x100
#define DBG_M_ONCE 0x200
#define DBG_M_KEEP 0x400
+#define DBG_M_WQ DI_BIT14 /*work que*/
extern unsigned int di_dbg;
#define dbg_dbg(fmt, args ...) dbg_m(DBG_M_DBG, fmt, ##args)
#define dbg_once(fmt, args ...) dbg_m(DBG_M_ONCE, fmt, ##args)
#define dbg_keep(fmt, args ...) dbg_m(DBG_M_KEEP, fmt, ##args)
+#define dbg_wq(fmt, args ...) dbg_m(DBG_M_WQ, fmt, ##args)
char *di_cfgx_get_name(enum eDI_CFGX_IDX idx);
bool di_cfgx_get(unsigned int ch, enum eDI_CFGX_IDX idx);
[eDI_CFG_BEGIN] = {"cfg top begin ", eDI_CFG_BEGIN, 0},
[eDI_CFG_first_bypass] = {"first_bypass",
- eDI_CFG_first_bypass, 1},
+ eDI_CFG_first_bypass, 0},
[eDI_CFG_ref_2] = {"ref_2",
eDI_CFG_ref_2, 0},
[EDI_CFG_KEEP_CLEAR_AUTO] = {"keep_buf clear auto",
- EDI_CFG_KEEP_CLEAR_AUTO, 1},
+ EDI_CFG_KEEP_CLEAR_AUTO, 0},
[eDI_CFG_END] = {"cfg top end ", eDI_CFG_END, 0},
};
unsigned int ch = wq->ch;
- pr_info("%s:ch[%d],start\n", __func__, ch);
-
do_flg = false;
cma_st = dip_cma_get_st(ch);
+ dbg_wq("%s:ch[%d],cmd[%d],st[%d]\n",
+ __func__, ch, pbm->cma_reg_cmd[ch], cma_st);
switch (cma_st) {
case EDI_CMA_ST_IDL:
if (pbm->cma_reg_cmd[ch]) {
break;
}
if (!do_flg)
- pr_info("\tch[%d],do nothing[%d]\n", ch, cma_st);
+ PR_INF("\tch[%d],do nothing[%d]\n", ch, cma_st);
else
task_send_ready();
- pr_info("%s:end\n", __func__);
+ dbg_wq("%s:end\n", __func__);
}
static void dip_wq_prob(void)
{
struct di_mng_s *pbm = get_bufmng();
+ dbg_wq("%s:ch[%d] [%d]\n", __func__, ch, reg_cmd);
if (reg_cmd)
pbm->cma_reg_cmd[ch] = 1;
else
"do_alloc",
"READY",
"do_release",
+ "PART",
};
const char *di_cma_dbg_get_st_name(unsigned int ch)
{
enum eDI_CMA_ST st = dip_cma_get_st(ch);
- const char *p = "";
+ const char *p = "overflow";
- if (st <= EDI_CMA_ST_RELEASE)
+ if (st <= ARRAY_SIZE(di_cma_state_name))
p = di_cma_state_name[st];
return p;
}
struct di_post_stru_s *ppost;
struct di_pre_stru_s *ppre = get_pre_stru(ch);
- pr_info("%s:\n", __func__);
+ dbg_reg("%s:\n", __func__);
/*post*/
ppost = get_post_stru(ch);
PR_ERR("di:%s:buf in some que,ch[%d],qt[%d],qi[%d],bi[%d]\n",
__func__,
ch, qtype, di_buf->queue_index, di_buf->index);
- return false;
+ dump_stack();
+ di_buf->queue_index = -1;
}
q_index = pw_buf_2_qindex(ch, di_buf);