ARM: ux500: register all SSP and SPI blocks
authorLinus Walleij <linus.walleij@linaro.org>
Fri, 18 Oct 2013 08:25:52 +0000 (10:25 +0200)
committerLinus Walleij <linus.walleij@linaro.org>
Fri, 18 Oct 2013 12:55:44 +0000 (14:55 +0200)
This adds the SSP and SPI blocks to the device tree and makes
them active. Only this way can their clocks be properly gated
off at boot.

Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
arch/arm/boot/dts/ste-dbx5x0.dtsi

index 0fc634b1b50efe95e05cb53d58a7229e52df5b43..7da99fe497e13d59215b2bdd1b16a41fcd120c70 100644 (file)
                        interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       status = "disabled";
+                       clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
+                       clock-names = "ssp0clk", "apb_pclk";
+                       dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
+                              <&dma 8 0 0x0>; /* Logical - MemToDev */
+                       dma-names = "rx", "tx";
+               };
+
+               ssp@80003000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0x80003000 0x1000>;
+                       interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
+                       clock-names = "ssp1clk", "apb_pclk";
+                       dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
+                              <&dma 9 0 0x0>; /* Logical - MemToDev */
+                       dma-names = "rx", "tx";
+               };
+
+               spi@8011a000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0x8011a000 0x1000>;
+                       interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       /* Same clock wired to kernel and pclk */
+                       clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
+                       clock-names = "spi0clk", "apb_pclk";
+                       dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
+                              <&dma 0 0 0x0>; /* Logical - MemToDev */
+                       dma-names = "rx", "tx";
+               };
+
+               spi@80112000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0x80112000 0x1000>;
+                       interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       /* Same clock wired to kernel and pclk */
+                       clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
+                       clock-names = "spi1clk", "apb_pclk";
+                       dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
+                              <&dma 35 0 0x0>; /* Logical - MemToDev */
+                       dma-names = "rx", "tx";
+               };
+
+               spi@80111000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0x80111000 0x1000>;
+                       interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       /* Same clock wired to kernel and pclk */
+                       clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
+                       clock-names = "spi2clk", "apb_pclk";
+                       dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
+                              <&dma 33 0 0x0>; /* Logical - MemToDev */
+                       dma-names = "rx", "tx";
+               };
+
+               spi@80129000 {
+                       compatible = "arm,pl022", "arm,primecell";
+                       reg = <0x80129000 0x1000>;
+                       interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       /* Same clock wired to kernel and pclk */
+                       clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
+                       clock-names = "spi3clk", "apb_pclk";
+                       dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
+                              <&dma 40 0 0x0>; /* Logical - MemToDev */
+                       dma-names = "rx", "tx";
                };
 
                uart@80120000 {