clk: si5351: Add PLL soft reset

This is according to figure 12 ("I2C Programming Procedure") in
"Si5351A/B/C Data Sheet"
(https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf).

Without the PLL soft reset, we were unable to get three outputs
working at the same time.

According to Silicon Labs support, performing PLL soft reset will only
be noticeable if the PLL parameters have been changed.

Signed-off-by: Jacob Siverskog <jacob@teenage.engineering>
Signed-off-by: Jens Rudberg <jens@teenage.engineering>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index e346b223199d5a5f742cd783f01fcb588b9f1b9f..850316ac88317a485dd77e8811dac736ce8da6ac 100644 (file)
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -1091,6 +1091,13 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
        si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
                        SI5351_CLK_POWERDOWN, 0);
 
+       /*
+        * Do a pll soft reset on both plls, needed in some cases to get
+        * all outputs running.
+        */
+       si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
+                        SI5351_PLL_RESET_A | SI5351_PLL_RESET_B);
+
        dev_dbg(&hwdata->drvdata->client->dev,
                "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
                __func__, clk_hw_get_name(hw), (1 << rdiv),