net/mlx5e: Update MPWQE stride size when modifying CQE compress state
authorSaeed Mahameed <saeedm@mellanox.com>
Wed, 22 Feb 2017 15:20:15 +0000 (17:20 +0200)
committerDavid S. Miller <davem@davemloft.net>
Thu, 23 Feb 2017 15:43:10 +0000 (10:43 -0500)
When the admin enables/disables cqe compression, updating
mpwqe stride size is required:
    CQE compress ON  ==> stride size = 256B
    CQE compress OFF ==> stride size = 64B

This is already done on driver load via mlx5e_set_rq_type_params, all we
need is just to call it on arbitrary admin changes of cqe compression
state via priv flags or when changing timestamping state
(as it is mutually exclusive with cqe compression).

This bug introduces no functional damage, it only makes cqe compression
occur less often, since in ConnectX4-LX CQE compression is performed
only on packets smaller than stride size.

Tested:
 ethtool --set-priv-flags ethxx rx_cqe_compress on
 pktgen with  64 < pkt size < 256 and netperf TCP_STREAM (IPv4/IPv6)
 verify `ethtool -S ethxx | grep compress` are advancing more often
 (rapidly)

Fixes: 7219ab34f184 ("net/mlx5e: CQE compression")
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
Cc: kernel-team@fb.com
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/mellanox/mlx5/core/en.h
drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

index 95ca03c0d9f54b543e3527fd7b80cebdb8d76d73..f6a6ded204f61cda53c6233d80b3db7cde678c6e 100644 (file)
@@ -816,6 +816,7 @@ int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
 
 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
                                 u8 cq_period_mode);
+void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type);
 
 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
                                      struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
index cc80522b585429c56c0836e6d1a035573cc146e7..a004a5a1a4c22a742ef3f9939769c6b5c9445f46 100644 (file)
@@ -1487,6 +1487,7 @@ static int set_pflag_rx_cqe_compress(struct net_device *netdev,
 
        mlx5e_modify_rx_cqe_compression_locked(priv, enable);
        priv->params.rx_cqe_compress_def = enable;
+       mlx5e_set_rq_type_params(priv, priv->params.rq_wq_type);
 
        return 0;
 }
index dc621bc4e173a14686c531b05719fa64fea51ad0..8ef64c4db2c21ad6a752338cb32b054a5e5f3968 100644 (file)
@@ -79,7 +79,7 @@ static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
                MLX5_CAP_ETH(mdev, reg_umr_sq);
 }
 
-static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
+void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
 {
        priv->params.rq_wq_type = rq_type;
        priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
index 9fad22768aab9e8180e5ec4d5bc8ebc05ad0c48f..d5ce20db3f0bb953342da80cf218abb9b448f27a 100644 (file)
@@ -172,6 +172,7 @@ void mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val)
                mlx5e_close_locked(priv->netdev);
 
        MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, val);
+       mlx5e_set_rq_type_params(priv, priv->params.rq_wq_type);
 
        if (was_opened)
                mlx5e_open_locked(priv->netdev);