{
unsigned gpio, bank;
int irq;
+ int ret;
struct clk *clk;
u32 binten = 0;
unsigned ngpio, bank_irq;
PTR_ERR(clk));
return PTR_ERR(clk);
}
- clk_prepare_enable(clk);
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ return ret;
if (!pdata->gpio_unbanked) {
irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
if (irq < 0) {
dev_err(dev, "Couldn't allocate IRQ numbers\n");
+ clk_disable_unprepare(clk);
return irq;
}
chips);
if (!irq_domain) {
dev_err(dev, "Couldn't register an IRQ domain\n");
+ clk_disable_unprepare(clk);
return -ENODEV;
}
}
sizeof(struct
davinci_gpio_irq_data),
GFP_KERNEL);
- if (!irqdata)
+ if (!irqdata) {
+ clk_disable_unprepare(clk);
return -ENOMEM;
+ }
irqdata->regs = g;
irqdata->bank_num = bank;