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OMAPDSS: DSI: Add FEAT_DSI_PLL_REFSEL
author
Tomi Valkeinen
<tomi.valkeinen@ti.com>
Wed, 22 Aug 2012 13:00:40 +0000
(16:00 +0300)
committer
Tomi Valkeinen
<tomi.valkeinen@ti.com>
Mon, 24 Sep 2012 13:50:09 +0000
(16:50 +0300)
Add FEAT_DSI_PLL_REFSEL. OMAP5's DSI PLL needs configuration to select
the reference clock to be used. We always use SYSCLK.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
drivers/video/omap2/dss/dsi.c
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drivers/video/omap2/dss/dss_features.c
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drivers/video/omap2/dss/dss_features.h
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diff --git
a/drivers/video/omap2/dss/dsi.c
b/drivers/video/omap2/dss/dsi.c
index 0c3afc2b4696ff1b61de0f4c41b165fdadc5dba0..a16c8b229ea717544d3057a8c21cef8f5f877f1c 100644
(file)
--- a/
drivers/video/omap2/dss/dsi.c
+++ b/
drivers/video/omap2/dss/dsi.c
@@
-1690,6
+1690,8
@@
int dsi_pll_set_clock_div(struct platform_device *dsidev,
l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
+ if (dss_has_feature(FEAT_DSI_PLL_REFSEL))
+ l = FLD_MOD(l, 3, 22, 21); /* REF_SYSCLK = sysclk */
dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
diff --git
a/drivers/video/omap2/dss/dss_features.c
b/drivers/video/omap2/dss/dss_features.c
index 177f6e8d2d7c7474492b4974fd5bcd2958c1ddcf..46855316d215e5f114166b569a7f2208352e9284 100644
(file)
--- a/
drivers/video/omap2/dss/dss_features.c
+++ b/
drivers/video/omap2/dss/dss_features.c
@@
-520,6
+520,7
@@
static const enum dss_feat_id omap5_dss_feat_list[] = {
FEAT_FIFO_MERGE,
FEAT_BURST_2D,
FEAT_DSI_PLL_SELFREQDCO,
+ FEAT_DSI_PLL_REFSEL,
};
/* OMAP2 DSS Features */
diff --git
a/drivers/video/omap2/dss/dss_features.h
b/drivers/video/omap2/dss/dss_features.h
index f9b9d28ed312b0765a7de519861ea2f636257673..0020bf66f3f5807d7ce0215c4a175a6eaace53d4 100644
(file)
--- a/
drivers/video/omap2/dss/dss_features.h
+++ b/
drivers/video/omap2/dss/dss_features.h
@@
-66,6
+66,7
@@
enum dss_feat_id {
FEAT_OMAP3_DSI_FIFO_BUG,
FEAT_BURST_2D,
FEAT_DSI_PLL_SELFREQDCO,
+ FEAT_DSI_PLL_REFSEL,
};
/* DSS register field id */