usb: phy: samsung: Add support HSIC on Exynos4X12
authorDongjin Kim <tobetter@gmail.com>
Tue, 21 May 2013 17:01:46 +0000 (02:01 +0900)
committerFelipe Balbi <balbi@ti.com>
Tue, 28 May 2013 17:16:37 +0000 (20:16 +0300)
This patch adds to enable High Speed Inter Chip on Exynos4X12. Both channels
are controlled by usbphy driver based on the patch series of usbphy driver
submitted by Tomasz Figa.

[1] https://patchwork.kernel.org/patch/2576121
[2] https://patchwork.kernel.org/patch/2576131
[3] https://patchwork.kernel.org/patch/2576141
[4] https://patchwork.kernel.org/patch/2576151
[5] https://patchwork.kernel.org/patch/2576161
[6] https://patchwork.kernel.org/patch/2576171

Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
drivers/usb/phy/phy-samsung-usb.c
drivers/usb/phy/phy-samsung-usb.h
drivers/usb/phy/phy-samsung-usb2.c

index 7a1ed90bd58e97994c8c2c6fedfea9031bdcbfd7..ac025ca08425eec5d912bd228f59d73bc2b40b4f 100644 (file)
@@ -100,6 +100,11 @@ void samsung_usbphy_set_isolation_4210(struct samsung_usbphy *sphy, bool on)
                reg_val |= en_mask;
 
        writel(reg_val, reg);
+
+       if (sphy->drv_data->cpu_type == TYPE_EXYNOS4X12) {
+               writel(reg_val, sphy->pmuregs + EXYNOS4X12_PHY_HSIC_CTRL0);
+               writel(reg_val, sphy->pmuregs + EXYNOS4X12_PHY_HSIC_CTRL1);
+       }
 }
 EXPORT_SYMBOL_GPL(samsung_usbphy_set_isolation_4210);
 
index 585d12f5c04428da8b4775d40d0bac4fafafb002..68771bfd18253df19dd2f999086611d0314d4b90 100644 (file)
 #define RSTCON_HLINK_SWRST                     (0x1 << 1)
 #define RSTCON_SWRST                           (0x1 << 0)
 
+/* EXYNOS4X12 */
+#define EXYNOS4X12_PHY_HSIC_CTRL0              (0x04)
+#define EXYNOS4X12_PHY_HSIC_CTRL1              (0x08)
+
+#define PHYPWR_NORMAL_MASK_HSIC1               (0x7 << 12)
+#define PHYPWR_NORMAL_MASK_HSIC0               (0x7 << 9)
+#define PHYPWR_NORMAL_MASK_PHY1                        (0x7 << 6)
+
+#define RSTCON_HOSTPHY_SWRST                   (0xf << 3)
+
 /* EXYNOS5 */
 #define EXYNOS5_PHY_HOST_CTRL0                 (0x00)
 
index 03180c06bfca088968dd5e345642797a0b722bba..1011c16ade7e4b2de81db46d0ab8ddfc599b24bc 100644 (file)
@@ -176,8 +176,12 @@ static void samsung_usb2phy_enable(struct samsung_usbphy *sphy)
                phypwr &= ~PHYPWR_NORMAL_MASK;
                rstcon |= RSTCON_SWRST;
                break;
-       case TYPE_EXYNOS4210:
        case TYPE_EXYNOS4X12:
+               phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 |
+                               PHYPWR_NORMAL_MASK_HSIC1 |
+                               PHYPWR_NORMAL_MASK_PHY1);
+               rstcon |= RSTCON_HOSTPHY_SWRST;
+       case TYPE_EXYNOS4210:
                phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
                rstcon |= RSTCON_SWRST;
        default:
@@ -190,6 +194,8 @@ static void samsung_usb2phy_enable(struct samsung_usbphy *sphy)
        /* reset all ports of PHY and Link */
        writel(rstcon, regs + SAMSUNG_RSTCON);
        udelay(10);
+       if (sphy->drv_data->cpu_type == TYPE_EXYNOS4X12)
+               rstcon &= ~RSTCON_HOSTPHY_SWRST;
        rstcon &= ~RSTCON_SWRST;
        writel(rstcon, regs + SAMSUNG_RSTCON);
 }
@@ -240,8 +246,11 @@ static void samsung_usb2phy_disable(struct samsung_usbphy *sphy)
        case TYPE_S3C64XX:
                phypwr |= PHYPWR_NORMAL_MASK;
                break;
-       case TYPE_EXYNOS4210:
        case TYPE_EXYNOS4X12:
+               phypwr |= (PHYPWR_NORMAL_MASK_HSIC0 |
+                               PHYPWR_NORMAL_MASK_HSIC1 |
+                               PHYPWR_NORMAL_MASK_PHY1);
+       case TYPE_EXYNOS4210:
                phypwr |= PHYPWR_NORMAL_MASK_PHY0;
        default:
                break;