dsim_phy_write_mask(id, 0x077c, 0x2, (0xffff << 0));
}
#endif
-#if 0
-/* DPHY setting */
-static void dsim_reg_set_pll_freq(u32 id, u32 p, u32 m, u32 s)
-{
- u32 val, mask;
- /* P value */
- val = DSIM_PHY_PMS_P(p);
- mask = DSIM_PHY_PMS_P_MASK;
- dsim_phy_write_mask(id, DSIM_PHY_PLL_CON0, val, mask);
-
- /* M value */
- val = DSIM_PHY_PMS_M(m);
- mask = DSIM_PHY_PMS_M_MASK;
- dsim_phy_write_mask(id, DSIM_PHY_PLL_CON2, val, mask);
-
- /* S value */
- val = DSIM_PHY_PMS_S(s);
- mask = DSIM_PHY_PMS_S_MASK;
- dsim_phy_write_mask(id, DSIM_PHY_PLL_CON0, val, mask);
-}
-#else
void dsim_reg_set_pll_freq(u32 id, u32 p, u32 m, u32 s)
{
u32 val = (p & 0x3f) << 13 | (m & 0x3ff) << 3 | (s & 0x7) << 0;
dsim_write_mask(id, DSIM_PLLCTRL, val, DSIM_PLLCTRL_PMS_MASK);
}
-#endif
void dsim_reg_set_dphy_timing_values(u32 id, struct dphy_timing_value *t)
{
dsim_phy_write_mask(id, DSIM_PHY_PLL_CON4, val, mask);
}
#endif
-#if 0
-/* PLL Control Register */
-static void dsim_reg_set_pll_con(u32 id, u32 *blk_ctl)
-{
- u32 i;
-
- for (i = 0; i < 8; i++)
- dsim_phy_write(id, DSIM_PHY_PLL_CON(i), blk_ctl[i]);
-}
-#endif
#ifdef DPDN_INV_SWAP
void dsim_reg_set_inv_dpdn(u32 id, u32 inv_clk, u32 inv_data[4])
{
#endif
/******************* DSIM CAL functions *************************/
+void dsim_reg_set_ppi(u32 id, enum dsim_ppi ppi)
+{
+ u32 val = (ppi == DSIM_2BYTEPPI) ? ~0 : 0;
+ u32 mask = DSIM_CSIS_LB_1BYTEPPI_MODE;
+
+ dsim_write_mask(id, DSIM_CSIS_LB, val, mask);
+}
+
static void dsim_reg_sw_reset(u32 id)
{
u32 cnt = 1000;
dsim_err("%s is timeout.\n", __func__);
}
-/* this function may be used for later use */
-static void dsim_reg_dphy_resetn(u32 id, u32 en)
+void dsim_reg_dphy_reset(u32 id)
+{
+ dsim_write_mask(id, DSIM_SWRST, 0, DSIM_DPHY_RST); /* reset low */
+ dsim_write_mask(id, DSIM_SWRST, ~0, DSIM_DPHY_RST); /* reset release */
+}
+
+void dsim_reg_dphy_resetn(u32 id, u32 en)
{
u32 val = en ? ~0 : 0;
dsim_write_mask(id, DSIM_CONFIG, val, DSIM_CONFIG_LANES_EN(lane));
}
-#if 0
-/*
- * lane_id : 0 = MC, 1 = MD0, 2 = MD1, 3 = MD2, 4 = MD3
- */
-static int dsim_reg_wait_phy_ready(u32 id, u32 lane_id, u32 en)
-{
- u32 ready, reg_id, val;
- u32 cnt = 1000;
-
- if (lane_id == 0)
- reg_id = DSIM_PHY_MC_GNR_CON0;
- else
- reg_id = DSIM_PHY_MD_GNR_CON0(lane_id-1);
-
- do {
- val = dsim_phy_read(id, reg_id);
- ready = DSIM_PHY_PHY_READY_GET(val);
- /* enable case */
- if ((en == 1) && (ready == 1))
- break;
- /* disable case */
- if ((en == 0) && (ready == 0))
- break;
-
- cnt--;
- udelay(10);
- } while (cnt);
-
- if (!cnt) {
- dsim_err("PHY lane(%d) is not ready[timeout]\n", lane_id);
- return -EBUSY;
- }
-
- return 0;
-}
-
-static int dsim_reg_enable_lane_phy(u32 id, u32 lane, u32 en)
-{
- u32 i, lane_cnt = 0;
- u32 reg_id;
- u32 ret = 0;
- u32 val = en ? ~0 : 0;
-
- /* check enabled data lane count */
- for (i = 0; i < MAX_DSIM_DATALANE_CNT; i++) {
- if ((lane >> i) & 0x1)
- lane_cnt++;
- }
-
- /*
- * [step1] enable phy_enable
- */
- /* (1.1) clock lane on|off */
- reg_id = DSIM_PHY_MC_GNR_CON0;
- dsim_phy_write_mask(id, reg_id, val, DSIM_PHY_PHY_ENABLE);
-
- /* (1.2) data lane on|off */
- for (i = 0; i < lane_cnt; i++) {
- reg_id = DSIM_PHY_MD_GNR_CON0(i);
- dsim_phy_write_mask(id, reg_id, val, DSIM_PHY_PHY_ENABLE);
- }
-
- /*
- * [step2] wait for phy_ready
- */
-
- /* (2.1) check ready of clock lane */
- if (dsim_reg_wait_phy_ready(id, 0, en))
- ret++;
-
- /* (2.2) check ready of data lanes (index : from '1') */
- for (i = 1; i <= lane_cnt; i++) {
- if (dsim_reg_wait_phy_ready(id, i, en))
- ret++;
- }
-
- if (ret) {
- dsim_err("Error to enable PHY lane(err=%d)\n", ret);
- return -EBUSY;
- } else
- return 0;
-}
-#endif
static void dsim_reg_pll_stable_time(u32 id)
{
dsim_write(id, DSIM_PLLTMR, DSIM_PLL_STABLE_TIME);
static void dsim_reg_set_pll(u32 id, u32 en)
{
u32 val = en ? ~0 : 0;
-#if 0
- dsim_phy_write_mask(id, DSIM_PHY_PLL_CON0, val, DSIM_PHY_PLL_EN_MASK);
-#else
+
dsim_write_mask(id, DSIM_PLLCTRL, val, DSIM_PLLCTRL_PLL_EN);
-#endif
}
static u32 dsim_reg_is_pll_stable(u32 id)
}
} else {
dsim_reg_set_pll(id, 0);
-#if 0
- while (1) {
- cnt--;
- if (!dsim_reg_is_pll_stable(id))
- return 0;
- if (cnt == 0)
- return -EBUSY;
- udelay(10);
- }
-#endif
}
return 0;
}
-static void dsim_reg_set_esc_clk_en(u32 id, u32 en)
-{
- u32 val = en ? ~0 : 0;
-
- dsim_write_mask(id, DSIM_CLK_CTRL, val, DSIM_CLK_CTRL_ESCCLK_EN);
-}
-
static void dsim_reg_set_esc_clk_prescaler(u32 id, u32 en, u32 p)
{
u32 val = en ? DSIM_CLK_CTRL_ESCCLK_EN : 0;
/*
* Following functions will not be used untile the correct guide is given.
*/
-static void dsim_reg_set_pll_clk_gate_enable(u32 id, u32 en)
-{
- u32 ver, mask, reg_id;
- u32 val = en ? ~0 : 0;
-
- ver = dsim_read(id, DSIM_VERSION);
- if (ver == DSIM_VER_EVT0) {
- reg_id = 0x0200;
- mask = 0x1;
- } else {
- reg_id = DSIM_CONFIG;
- mask = DSIM_CONFIG_PLL_CLOCK_GATING;
- }
- dsim_write_mask(id, reg_id, val, mask);
-}
-
-#if 0
-/* This function is available from EVT1 */
-static void dsim_reg_set_pll_sleep_enable(u32 id, u32 en)
-{
- u32 val = en ? ~0 : 0;
-
- dsim_write_mask(id, DSIM_CONFIG, val, DSIM_CONFIG_PLL_SLEEP);
-}
-#endif
-
-/* 0=D-PHY, 1=C-PHY */
-void dsim_reg_set_phy_selection(u32 id, u32 sel)
-{
- u32 val = sel ? ~0 : 0;
-
- dsim_write_mask(id, DSIM_CONFIG, val, DSIM_CONFIG_PHY_SELECTION);
-}
-
static void dsim_reg_set_vfp(u32 id, u32 vfp)
{
u32 val = DSIM_VPORCH_VFP_TOTAL(vfp);
dsim_write_mask(id, DSIM_CONFIG, val, DSIM_CONFIG_VIDEO_MODE);
}
-static int dsim_reg_wait_idle_status(u32 id, u32 is_vm)
-{
- u32 cnt = 1000;
- u32 reg_id, val, status;
-
- if (is_vm)
- reg_id = DSIM_LINK_STATUS0;
- else
- reg_id = DSIM_LINK_STATUS1;
-
- do {
- val = dsim_read(id, reg_id);
- status = is_vm ? DSIM_LINK_STATUS0_VIDEO_MODE_STATUS_GET(val) :
- DSIM_LINK_STATUS1_CMD_MODE_STATUS_GET(val);
- if (status == DSIM_STATUS_IDLE)
- break;
- cnt--;
- udelay(10);
- } while (cnt);
-
- if (!cnt) {
- dsim_err("dsim%d wait timeout idle status(%u)\n", id, status);
- return -EBUSY;
- }
-
- return 0;
-}
-
-/* 0 = command, 1 = video mode */
-static u32 dsim_reg_get_display_mode(u32 id)
-{
- u32 val;
-
- val = dsim_read(id, DSIM_CONFIG);
- return DSIM_CONFIG_DISPLAY_MODE_GET(val);
-}
-
static void dsim_reg_enable_dsc(u32 id, u32 en)
{
u32 val = en ? ~0 : 0;
dsim_write_mask(id, DSIM_CLK_CTRL, val, DSIM_CLK_CTRL_CLOCK_SEL);
}
-static int dsim_reg_get_link_clock(u32 id)
-{
- int val = 0;
-
- val = dsim_read_mask(id, DSIM_CLK_CTRL, DSIM_CLK_CTRL_CLOCK_SEL);
-
- return val;
-}
-
static void dsim_reg_enable_hs_clock(u32 id, u32 en)
{
u32 val = en ? ~0 : 0;
dsim_reg_set_bta_timeout(id);
dsim_reg_set_lpdr_timeout(id);
-
- dsim_reg_set_cmd_transfer_mode(id, 0);
dsim_reg_set_stop_state_cnt(id);
if (lcd_info->mode == DECON_MIPI_COMMAND_MODE) {
dsim_reg_set_vstatus_int(id, DSIM_VSYNC);
}
+ dsim_reg_set_ppi(id, DSIM_1BYTEPPI);
/* dsim_reg_enable_shadow_read(id, 1); */
/* dsim_reg_enable_shadow(id, 1); */
struct dphy_timing_value t;
int ret = 0;
u32 hsmode = 0;
-#ifdef DPDN_INV_SWAP
- u32 inv_data[4] = {0, };
-#endif
if (en) {
/*
clks->esc_clk = clks->word_clk / esc_div;
dsim_dbg("escape clock divider is 0x%x\n", esc_div);
dsim_dbg("escape clock is %u MHz\n", clks->esc_clk);
-#if 0
- /* set PLL ctrl : default value */
- dsim_reg_set_pll_con(id, DSIM_PHY_PLL_CON_VAL);
-#endif
+
if (clks->hs_clk < 1500)
hsmode = 1;
dsim_reg_set_esc_clk_prescaler(id, 1, esc_div);
/* get DPHY timing values using hs clock and escape clock */
+
dsim_reg_get_dphy_timing(clks->hs_clk, clks->esc_clk, &t);
dsim_reg_set_dphy_timing_values(id, &t);
-#if defined(CONFIG_EXYNOS_DSIM_DITHER)
- /* check dither sequence */
- dsim_reg_set_dphy_param_dither(id, dphy_pms);
- dsim_reg_set_dphy_dither_en(id, 1);
-#endif
+
dsim_reg_set_m_pll_ctrl1(id, DSIM_PHY_CHARIC_VAL[id][M_PLL_CTRL1]);
dsim_reg_set_m_pll_ctrl2(id, DSIM_PHY_CHARIC_VAL[id][M_PLL_CTRL2]);
dsim_reg_set_b_dphy_ctrl2(id, DSIM_PHY_CHARIC_VAL[id][B_DPHY_CTRL2]);
return 0;
}
-#if 0
-static int dsim_reg_set_lanes_dphy(u32 id, u32 lanes, u32 en)
-{
- /* PHY lanes */
- if (dsim_reg_enable_lane_phy(id, (lanes >> 1), en))
- return -EBUSY;
- return 0;
-}
-#endif
static u32 dsim_reg_is_noncont_clk_enabled(u32 id)
{
int ret;
}
/******************** EXPORTED DSIM CAL APIs ********************/
-void dpu_sysreg_set_dphy(struct dsim_device *dsim, void __iomem *sysreg)
-{
- u32 val;
-
- val = SEL_RESET_DPHY_MASK(dsim->id);
- writel(val, sysreg + DISP_DPU_MIPI_PHY_CON);
-}
-
-void dsim_reg_dphy_reset(u32 id)
-{
- dsim_write_mask(id, DSIM_SWRST, 0, DSIM_DPHY_RST); /* reset low */
- dsim_write_mask(id, DSIM_SWRST, ~0, DSIM_DPHY_RST); /* reset release */
-}
void dpu_sysreg_select_dphy_rst_control(void __iomem *sysreg, u32 dsim_id, u32 sel)
{
+#if 1
u32 phy_num = dsim_id ? 0 : 1;
u32 old = readl(sysreg + DISP_DPU_MIPI_PHY_CON);
u32 val = sel ? ~0 : 0;
val = (val & mask) | (old & ~mask);
writel(val, sysreg + DISP_DPU_MIPI_PHY_CON);
-}
-
-void dpu_sysreg_dphy_reset(void __iomem *sysreg, u32 dsim_id, u32 rst)
-{
- u32 old = readl(sysreg + DISP_DPU_MIPI_PHY_CON);
- u32 val = rst ? ~0 : 0;
- u32 mask = dsim_id ? M_RESETN_M4S4_TOP_MASK : M_RESETN_M4S4_MODULE_MASK;
+#else
+ u32 val;
- val = (val & mask) | (old & ~mask);
+ val = SEL_RESET_DPHY_MASK(dsim_id);
writel(val, sysreg + DISP_DPU_MIPI_PHY_CON);
-}
-
-static u32 dsim_reg_translate_lanecnt_to_lanes(int lanecnt)
-{
- u32 lanes, i;
-
- lanes = DSIM_LANE_CLOCK;
- for (i = 1; i <= lanecnt; ++i)
- lanes |= 1 << i;
-
- return lanes;
+#endif
}
void dsim_reg_init(u32 id, struct decon_lcd *lcd_info, struct dsim_clks *clks,
bool panel_ctrl)
{
- u32 lanes;
-#if !defined(CONFIG_EXYNOS_LCD_ON_UBOOT)
struct dsim_device *dsim = get_dsim_drvdata(id);
-#endif
if (dsim->state == DSIM_STATE_INIT) {
- if (dsim_reg_get_link_clock(dsim->id)) {
- dsim_info("dsim%d is already enabled in bootloader\n", dsim->id);
+ if (dsim_reg_is_pll_stable(dsim->id)) {
+ dsim_info("dsim%d PLL is stabled in bootloader, so skip DSIM link/DPHY init.\n", dsim->id);
return;
}
}
- lanes = dsim_reg_translate_lanecnt_to_lanes(lcd_info->data_lane);
-
/* choose OSC_CLK */
dsim_reg_set_link_clock(id, 0);
+ /* Enable DPHY reset : DPHY reset start */
+ dsim_reg_dphy_resetn(dsim->id, 0);
dsim_reg_sw_reset(id);
- dsim_reg_set_lanes(id, lanes, 1);
-
- dsim_reg_set_esc_clk_on_lane(id, 1, lanes);
-
- dsim_reg_set_pll_clk_gate_enable(id, 1);
+ dsim_reg_set_clocks(id, clks, &lcd_info->dphy_pms, 1);
+ dsim_reg_set_lanes(id, dsim->data_lane, 1);
+ dsim_reg_dphy_resetn(dsim->id, 1); /* Release DPHY reset */
+ dsim_reg_set_link_clock(id, 1); /* Selection to word clock */
+ dsim_reg_set_esc_clk_on_lane(id, 1, dsim->data_lane);
dsim_reg_enable_word_clock(id, 1);
- /* Enable DPHY reset : DPHY reset start */
-// dpu_sysreg_dphy_reset(dsim->res.ss_regs, id, 0);
- dsim_reg_dphy_resetn(dsim->id, 0);
-
-#if defined(CONFIG_EXYNOS_LCD_ON_UBOOT)
- /* TODO: This code will be implemented as uboot style */
-#else
/* Panel power on */
if (panel_ctrl)
dsim_set_panel_power(dsim, 1);
-#endif
-
- dsim_reg_set_clocks(id, clks, &lcd_info->dphy_pms, 1);
-
- //dsim_reg_set_lanes_dphy(id, lanes, 1);
-// dpu_sysreg_dphy_reset(dsim->res.ss_regs, id, 1); /* Release DPHY reset */
- dsim_reg_dphy_resetn(dsim->id, 1);
- dsim_reg_sw_reset(id);
- dsim_reg_set_lanes(id, lanes, 1);
-
- dsim_reg_set_link_clock(id, 1); /* Selection to word clock */
dsim_reg_set_config(id, lcd_info, clks);
- dsim_reg_set_pll_clk_gate_enable(id, 0); /* phy clockgate enable */
- dsim_reg_set_pll_clk_gate_enable(id, 1); /* phy clockgate disable */
-
-#if defined(CONFIG_EXYNOS_LCD_ON_UBOOT)
- /* TODO: This code will be implemented as uboot style */
-#else
if (panel_ctrl)
dsim_reset_panel(dsim);
-#endif
}
/* Set clocks and lanes and HS ready */
int dsim_reg_stop(u32 id, u32 lanes)
{
int err = 0;
-#if 0
- u32 is_vm;
-#endif
- struct dsim_device *dsim = get_dsim_drvdata(id);
dsim_reg_clear_int(id, 0xffffffff);
/* disable interrupts */
/* first disable HS clock */
if (dsim_reg_set_hs_clock(id, 0) < 0)
dsim_err("The CLK lane doesn't be switched to LP mode\n");
-#if 0
- /* 0. wait the IDLE status */
- is_vm = dsim_reg_get_display_mode(id);
- err = dsim_reg_wait_idle_status(id, is_vm);
- if (err < 0)
- dsim_err("DSIM status is not IDLE!\n");
-#endif
- /* 1. clock selection : OSC */
- dsim_reg_set_link_clock(id, 0);
- /* 2. master resetn */
- dpu_sysreg_dphy_reset(dsim->res.ss_regs, id, 0);
- /* 3. disable lane */
- //dsim_reg_set_lanes_dphy(id, lanes, 0);
- /* 4. turn off WORDCLK and ESCCLK */
+ /* clock selection : OSC */
+ dsim_reg_set_link_clock(id, 0);
+ dsim_reg_set_lanes(id, lanes, 0);
dsim_reg_set_esc_clk_on_lane(id, 0, lanes);
- dsim_reg_set_esc_clk_en(id, 0);
- /* 5. disable PLL */
+ dsim_reg_enable_word_clock(id, 0);
dsim_reg_set_clocks(id, NULL, NULL, 0);
-
- if (err == 0)
- dsim_reg_sw_reset(id);
+ dsim_reg_sw_reset(id);
return err;
}
int dsim_reg_stop_and_enter_ulps(u32 id, u32 ddi_type, u32 lanes)
{
int ret = 0;
- u32 is_vm;
- struct dsim_device *dsim = get_dsim_drvdata(id);
-
- dsim_reg_clear_int(id, 0xffffffff);
- /* disable interrupts */
- dsim_reg_set_int(id, 0);
- /* 1. turn off clk lane & wait for stopstate_clk */
ret = dsim_reg_set_hs_clock(id, 0);
if (ret < 0)
dsim_err("The CLK lane doesn't be switched to LP mode\n");
- /* 2. enter to ULPS & wait for ulps state of clk and data */
dsim_reg_set_ulps_by_ddi(id, ddi_type, lanes, 1);
-
- /* 3. sequence for BLK_DPU off */
- /* 3.1 wait idle */
- is_vm = dsim_reg_get_display_mode(id);
- ret = dsim_reg_wait_idle_status(id, is_vm);
- if (ret < 0)
- dsim_err("%s : DSIM_status is not IDLE!\n", __func__);
- /* 3.2 OSC clock */
+ /* clock source to OSC */
dsim_reg_set_link_clock(id, 0);
- /* 3.3 off DPHY */
- dpu_sysreg_dphy_reset(dsim->res.ss_regs, id, 0);
- //dsim_reg_set_lanes_dphy(id, lanes, 0);
+ dsim_reg_set_lanes(id, lanes, 0);
+ dsim_reg_set_esc_clk_on_lane(id, 0, lanes);
+ /* 20161201 guide from DIP Team */
+ /* dsim_reg_enable_word_clock(id, 0); */
dsim_reg_set_clocks(id, NULL, NULL, 0);
- /* 3.4 sw reset */
dsim_reg_sw_reset(id);
-
return ret;
}
#define DSIM_LINK_STATUS1 (0xc)
#define DSIM_LINK_STATUS1_CMD_MODE_STATUS_GET(x) ((x >> 26) & 0x1)
-#define DSIM_STATUS_IDLE 0
-#define DSIM_STATUS_ACTIVE 1
-
#define DSIM_LINK_STATUS3 (0x14)
#define DSIM_LINK_STATUS3_PLL_STABLE (1 << 0)
/* Configuration register */
#define DSIM_CONFIG (0x4c)
-#define DSIM_CONFIG_PLL_CLOCK_GATING (1 << 30)
-#define DSIM_CONFIG_PLL_SLEEP (1 << 29)
-#define DSIM_CONFIG_PHY_SELECTION (1 << 28)
#define DSIM_CONFIG_SYNC_INFORM (1 << 27)
#define DSIM_CONFIG_BURST_MODE (1 << 26)
#define DSIM_CONFIG_LP_FORCE_EN (1 << 24)
#define DSIM_CONFIG_HSA_DISABLE (1 << 20)
#define DSIM_CONFIG_CPRS_EN (1 << 19)
#define DSIM_CONFIG_VIDEO_MODE (1 << 18)
-#define DSIM_CONFIG_DISPLAY_MODE_GET(_v) (((_v) >> 18) & 0x1)
#define DSIM_CONFIG_VC_ID(_x) ((_x) << 15)
#define DSIM_CONFIG_VC_ID_MASK (0x3 << 15)
#define DSIM_CONFIG_PIXEL_FORMAT(_x) ((_x) << 9)
#define DSIM_CONFIG_NUM_OF_DATA_LANE(_x) ((_x) << 5)
#define DSIM_CONFIG_NUM_OF_DATA_LANE_MASK (0x3 << 5)
#define DSIM_CONFIG_LANES_EN(_x) (((_x) & 0x1f) << 0)
-#define DSIM_CONFIG_CLK_LANES_EN (1 << 0)
/* Interrupt source register */
#define DSIM_INTSRC (0x50)
/* PLL control register */
#define DSIM_PLLCTRL (0xa0)
+#define DSIM_PLLCTRL_DPDN_SWAP_CLK (1 << 25)
+#define DSIM_PLLCTRL_DPDN_SWAP_DATA (1 << 24)
#define DSIM_PLLCTRL_PLL_EN (1 << 23)
#define DSIM_PLLCTRL_PMS_MASK (0x7ffff << 0)
-/* PLL timer register */
-#define DSIM_PLLTMR (0xac)
-
/* M_PLL CTR1 register*/
#define DSIM_PLL_CTRL1 (0xa4)
#define DSIM_PLL_CTRL1_M_PLL_CTRL1 (0xffffffff << 0)
#define DSIM_SA_CRC_RESULT_LN3_MASK (0xffff << 0)
#define DSIM_SA_CRC_RESULT_LN3_GET(x) (((x) >> 0) & 0xffff)
-
-/*
- * DPHY registers
- */
-
-/* MK */
-#define DCPHY_TOP_M4S4 0x0000
-#define DCPHY_MOD_M4S0 0x1000
-
-
-/* DPHY BIAS setting */
-#define DSIM_PHY_BIAS_CON(_id) (0x0000 + (4 * (_id)))
-
-/* DPHY PLL setting */
-#define DSIM_PHY_PLL_CON(_id) (0x0100 + (4 * (_id)))
-#define DSIM_PHY_PLL_CON0 (0x0100)
-#define DSIM_PHY_PLL_CON1 (0x0104)
-#define DSIM_PHY_PLL_CON2 (0x0108)
-#define DSIM_PHY_PLL_CON3 (0x010C)
-#define DSIM_PHY_PLL_CON4 (0x0110)
-#define DSIM_PHY_PLL_CON5 (0x0114)
-#define DSIM_PHY_PLL_CON6 (0x0118)
-#define DSIM_PHY_PLL_CON7 (0x011C)
-#define DSIM_PHY_PLL_STAT0 (0x0120)
-
-/* PLL_CON0 */
-#define DSIM_PHY_PLL_EN(_x) (((_x) & 0x1) << 12)
-#define DSIM_PHY_PLL_EN_MASK (0x1 << 12)
-#define DSIM_PHY_PMS_S(_x) (((_x) & 0x7) << 8)
-#define DSIM_PHY_PMS_S_MASK (0x7 << 8)
-#define DSIM_PHY_PMS_P(_x) (((_x) & 0x3f) << 0)
-#define DSIM_PHY_PMS_P_MASK (0x3f << 0)
-
-/* PLL_CON1 */
-#define DSIM_PHY_PMS_K(_x) (((_x) & 0xffff) << 0)
-#define DSIM_PHY_PMS_K_MASK (0xffff << 0)
-
-/* PLL_CON2 */
-#define DSIM_PHY_PMS_M(_x) (((_x) & 0x3ff) << 0)
-#define DSIM_PHY_PMS_M_MASK (0x3ff << 0)
-
-#if defined(CONFIG_EXYNOS_DSIM_DITHER)
-/* PLL_CON2 */
-#define DSIM_PHY_DITHER_FOUT_MASK (0x1 << 13)
-#define DSIM_PHY_DITHER_FEED_EN (0x1 << 12)
-/* PLL_CON3 */
-#define DSIM_PHY_DITHER_MRR(_x) (((_x) & 0x3f) << 8)
-#define DSIM_PHY_DITHER_MRR_MASK (0x3f << 8)
-#define DSIM_PHY_DITHER_MFR(_x) (((_x) & 0xff) << 0)
-#define DSIM_PHY_DITHER_MFR_MASK (0xff << 0)
-/* PLL_CON4 */
-#define DSIM_PHY_DITHER_RSEL(_x) (((_x) & 0xf) << 12)
-#define DSIM_PHY_DITHER_RSEL_MASK (0xf << 12)
-#define DSIM_PHY_DITHER_EN (0x1 << 11)
-#define DSIM_PHY_DITHER_FSEL (0x1 << 10)
-#define DSIM_PHY_DITHER_BYPASS (0x1 << 9)
-#define DSIM_PHY_DITHER_AFC_ENB (0x1 << 8)
-#define DSIM_PHY_DITHER_EXTAFC(_x) (((_x) & 0x1f) << 0)
-#define DSIM_PHY_DITHER_EXTAFC_MASK (0x1f << 0)
-/* PLL_CON5 */
-#define DSIM_PHY_DITHER_ICP(_x) (((_x) & 0x3) << 4)
-#define DSIM_PHY_DITHER_ICP_MASK (0x3 << 4)
-#define DSIM_PHY_DITHER_SEL_PF(_x) (((_x) & 0x3) << 0)
-#define DSIM_PHY_DITHER_SEL_PF_MASK (0x3 << 0)
-#endif
-
-/* PLL_CON6 */
-/*
- * WCLK_BUF_SFT_CNT = Roundup((Word Clock Period) / 38.46 + 2)
- */
-#define DSIM_PHY_WCLK_BUF_SFT_CNT(_x) (((_x) & 0xf) << 8)
-#define DSIM_PHY_WCLK_BUF_SFT_CNT_MASK (0xf << 8)
-/* PLL_CON7 */
-#define DSIM_PHY_PLL_LOCK_CNT(_x) (((_x) & 0xffff) << 0)
-#define DSIM_PHY_PLL_LOCK_CNT_MASK (0xffff << 0)
-/* PLL_STAT0 */
-#define DSIM_PHY_PLL_LOCK_GET(x) (((x) >> 0) & 0x1)
-
-/* master clock lane General Control Register : GNR */
-#define DSIM_PHY_MC_GNR_CON(_id) (0x0300 + (4 * (_id)))
-#define DSIM_PHY_MC_GNR_CON0 (0x0300)
-#define DSIM_PHY_MC_GNR_CON1 (0x0304)
-/* GNR0 */
-#define DSIM_PHY_PHY_READY (0x1 << 1)
-#define DSIM_PHY_PHY_READY_GET(x) (((x) >> 1) & 0x1)
-#define DSIM_PHY_PHY_ENABLE (0x1 << 0)
-/* GNR1 */
-#define DSIM_PHY_T_PHY_READY(_x) (((_x) & 0xffff) << 0)
-#define DSIM_PHY_T_PHY_READY_MASK (0xffff << 0)
-
-
-/* master clock lane Analog Block Control Register : ANA */
-#define DSIM_PHY_MC_ANA_CON(_id) (0x0308 + (4 * (_id)))
-#define DSIM_PHY_MC_ANA_CON0 (0x0308)
-#define DSIM_PHY_MC_ANA_CON1 (0x030C)
-
-#define DSIM_PHY_EDGE_CON_EN (0x1 << 8)
-#define DSIM_PHY_RES_UP(_x) (((_x) & 0xf) << 4)
-#define DSIM_PHY_RES_UP_MASK (0xf << 4)
-#define DSIM_PHY_RES_DN(_x) (((_x) & 0xf) << 0)
-#define DSIM_PHY_RES_DN_MASK (0xf << 0)
-
-#define DSIM_PHY_DPDN_SWAP(_x) (((_x) & 0x) << 12)
-#define DSIM_PHY_DPDN_SWAP_MASK (0x1 << 12)
-
-
-/* master clock lane setting */
-#define DSIM_PHY_MC_TIME_CON0 (0x0330)
-#define DSIM_PHY_MC_TIME_CON1 (0x0334)
-#define DSIM_PHY_MC_TIME_CON2 (0x0338)
-#define DSIM_PHY_MC_TIME_CON3 (0x033C)
-#define DSIM_PHY_MC_TIME_CON4 (0x0340)
-#define DSIM_PHY_MC_DATA_CON0 (0x0344)
-#define DSIM_PHY_MC_DESKEW_CON0 (0x0350)
-
-/*
- * master data lane setting : D0 ~ D3
- * D0~D2 : COMBO
- * D3 : DPHY
- */
-#define DSIM_PHY_MD_GNR_CON0(_x) (0x0400 + (0x100 * (_x)))
-#define DSIM_PHY_MD_GNR_CON1(_x) (0x0404 + (0x100 * (_x)))
-#define DSIM_PHY_MD_ANA_CON0(_x) (0x0408 + (0x100 * (_x)))
-#define DSIM_PHY_MD_ANA_CON1(_x) (0x040C + (0x100 * (_x)))
-#define DSIM_PHY_MD_ANA_CON2(_x) (0x0410 + (0x100 * (_x)))
-#define DSIM_PHY_MD_ANA_CON3(_x) (0x0414 + (0x100 * (_x)))
-#define DSIM_PHY_MD_TIME_CON0(_x) (0x0430 + (0x100 * (_x)))
-#define DSIM_PHY_MD_TIME_CON1(_x) (0x0434 + (0x100 * (_x)))
-#define DSIM_PHY_MD_TIME_CON2(_x) (0x0438 + (0x100 * (_x)))
-#define DSIM_PHY_MD_TIME_CON3(_x) (0x043C + (0x100 * (_x)))
-#define DSIM_PHY_MD_TIME_CON4(_x) (0x0440 + (0x100 * (_x)))
-#define DSIM_PHY_MD_DATA_CON0(_x) (0x0444 + (0x100 * (_x)))
-
-/* master data lane(COMBO) setting : D0 */
-#define DSIM_PHY_MD0_TIME_CON0 (0x0430)
-#define DSIM_PHY_MD0_TIME_CON1 (0x0434)
-#define DSIM_PHY_MD0_TIME_CON2 (0x0438)
-#define DSIM_PHY_MD0_TIME_CON3 (0x043C)
-#define DSIM_PHY_MD0_TIME_CON4 (0x0440)
-#define DSIM_PHY_MD0_DATA_CON0 (0x0444)
-
-/* master data lane(COMBO) setting : D1 */
-#define DSIM_PHY_MD1_TIME_CON0 (0x0530)
-#define DSIM_PHY_MD1_TIME_CON1 (0x0534)
-#define DSIM_PHY_MD1_TIME_CON2 (0x0538)
-#define DSIM_PHY_MD1_TIME_CON3 (0x053C)
-#define DSIM_PHY_MD1_TIME_CON4 (0x0540)
-#define DSIM_PHY_MD1_DATA_CON0 (0x0544)
-
-/* master data lane(COMBO) setting : D2 */
-#define DSIM_PHY_MD2_TIME_CON0 (0x0630)
-#define DSIM_PHY_MD2_TIME_CON1 (0x0634)
-#define DSIM_PHY_MD2_TIME_CON2 (0x0638)
-#define DSIM_PHY_MD2_TIME_CON3 (0x063C)
-#define DSIM_PHY_MD2_TIME_CON4 (0x0640)
-#define DSIM_PHY_MD2_DATA_CON0 (0x0644)
-
-/* master data lane setting : D3 */
-#define DSIM_PHY_MD3_TIME_CON0 (0x0730)
-#define DSIM_PHY_MD3_TIME_CON1 (0x0734)
-#define DSIM_PHY_MD3_TIME_CON2 (0x0738)
-#define DSIM_PHY_MD3_TIME_CON3 (0x073C)
-#define DSIM_PHY_MD3_TIME_CON4 (0x0740)
-#define DSIM_PHY_MD3_DATA_CON0 (0x0744)
-
-
-/* macros for DPHY timing controls */
-/* MC/MD_TIME_CON0 */
-#define DSIM_PHY_HSTX_CLK_SEL (0x1 << 12)
-#define DSIM_PHY_TLPX(_x) (((_x) & 0xff) << 4)
-#define DSIM_PHY_TLPX_MASK (0xff << 4)
-/* MD only */
-#define DSIM_PHY_TLP_EXIT_SKEW(_x) (((_x) & 0x3) << 2)
-#define DSIM_PHY_TLP_EXIT_SKEW_MASK (0x3 << 2)
-#define DSIM_PHY_TLP_ENTRY_SKEW(_x) (((_x) & 0x3) << 0)
-#define DSIM_PHY_TLP_ENTRY_SKEW_MASK (0x3 << 0)
-
-/* MC/MD_TIME_CON1 */
-#define DSIM_PHY_TCLK_ZERO(_x) (((_x) & 0xff) << 8)
-#define DSIM_PHY_TCLK_ZERO_MASK (0xff << 8)
-#define DSIM_PHY_TCLK_PREPARE(_x) (((_x) & 0xff) << 0)
-#define DSIM_PHY_TCLK_PREPARE_MASK (0xff << 0)
-/* MD case */
-#define DSIM_PHY_THS_ZERO(_x) (((_x) & 0xff) << 8)
-#define DSIM_PHY_THS_ZERO_MASK (0xff << 8)
-#define DSIM_PHY_THS_PREPARE(_x) (((_x) & 0xff) << 0)
-#define DSIM_PHY_THS_PREPARE_MASK (0xff << 0)
-
-/* MC/MD_TIME_CON2 */
-#define DSIM_PHY_THS_EXIT(_x) (((_x) & 0xff) << 8)
-#define DSIM_PHY_THS_EXIT_MASK (0xff << 8)
-#define DSIM_PHY_TCLK_TRAIL(_x) (((_x) & 0xff) << 0)
-#define DSIM_PHY_TCLK_TRAIL_MASK (0xff << 0)
-/* MD case */
-#define DSIM_PHY_THS_TRAIL(_x) (((_x) & 0xff) << 0)
-#define DSIM_PHY_THS_TRAIL_MASK (0xff << 0)
-
-/* MC_TIME_CON3 */
-#define DSIM_PHY_TCLK_POST(_x) (((_x) & 0xff) << 0)
-#define DSIM_PHY_TCLK_POST_MASK (0xff << 0)
-/* MD_TIME_CON3 */
-#define DSIM_PHY_TTA_GET(_x) (((_x) & 0xf) << 4)
-#define DSIM_PHY_TTA_GET_MASK (0xf << 4)
-#define DSIM_PHY_TTA_GO(_x) (((_x) & 0xf) << 0)
-#define DSIM_PHY_TTA_GO_MASK (0xf << 0)
-
-/* MC/MD_TIME_CON4 */
-#define DSIM_PHY_ULPS_EXIT(_x) (((_x) & 0x3ff) << 0)
-#define DSIM_PHY_ULPS_EXIT_MASK (0x3ff << 0)
-
-/* MC_DATA_CON0 */
-#define DSIM_PHY_CLK_INV (0x1 << 1)
-/* MC_DATA_CON0 */
-#define DSIM_PHY_DATA_INV (0x1 << 1)
-
-/* MC_DESKEW_CON0 */
-#define DSIM_PHY_SKEWCAL_RUN_TIME(_x) (((_x) & 0xf) << 12)
-#define DSIM_PHY_SKEWCAL_RUN_TIME_MASK (0xf << 12)
-#define DSIM_PHY_SKEWCAL_INIT_RUN_TIME(_x) (((_x) & 0xf) << 8)
-#define DSIM_PHY_SKEWCAL_INIT_RUN_TIME_MASK (0xf << 8)
-#define DSIM_PHY_SKEWCAL_INIT_WAIT_TIME(_x) (((_x) & 0xf) << 4)
-#define DSIM_PHY_SKEWCAL_INIT_WAIT_TIME_MASK (0xf << 4)
-#define DSIM_PHY_SKEWCAL_EN (0x1 << 0)
-
#endif /* _REGS_DSIM_H */
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff