drm/i915/bxt: fix dsi hw state pipe readout
authorJani Nikula <jani.nikula@intel.com>
Tue, 15 Mar 2016 19:51:12 +0000 (21:51 +0200)
committerJani Nikula <jani.nikula@intel.com>
Wed, 16 Mar 2016 16:10:54 +0000 (18:10 +0200)
BXT isn't as limited as BYT and CHT regarding DSI pipes and ports.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/8bea85b86aaf7a15f854a656bf8d3208a3afe0bd.1458070700.git.jani.nikula@intel.com
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_dsi.c

index 85ceec611412101204452e87caa6fc8706d9f772..d4a298f715f4e822b9fa9a0065b961b29f152ae4 100644 (file)
@@ -8144,6 +8144,7 @@ enum skl_disp_power_wells {
 #define  READ_REQUEST_PRIORITY_HIGH                    (3 << 3)
 #define  RGB_FLIP_TO_BGR                               (1 << 2)
 
+#define  BXT_PIPE_SELECT_SHIFT                         7
 #define  BXT_PIPE_SELECT_MASK                          (7 << 7)
 #define  BXT_PIPE_SELECT(pipe)                         ((pipe) << 7)
 
index 32606652bb58e712aeb8a63d66acd9a056731350..475634667222c2d4c4e3f8c96289a08b8ed22e53 100644 (file)
@@ -700,7 +700,19 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
                if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
                        continue;
 
-               *pipe = port == PORT_A ? PIPE_A : PIPE_B;
+               if (IS_BROXTON(dev_priv)) {
+                       u32 tmp = I915_READ(MIPI_CTRL(port));
+                       tmp &= BXT_PIPE_SELECT_MASK;
+                       tmp >>= BXT_PIPE_SELECT_SHIFT;
+
+                       if (WARN_ON(tmp > PIPE_C))
+                               continue;
+
+                       *pipe = tmp;
+               } else {
+                       *pipe = port == PORT_A ? PIPE_A : PIPE_B;
+               }
+
                active = true;
                break;
        }