drm/amdgpu: expand pte flags to uint64_t
authorChunming Zhou <David1.Zhou@amd.com>
Wed, 21 Sep 2016 08:19:19 +0000 (16:19 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 30 Mar 2017 03:53:38 +0000 (23:53 -0400)
Necessary for new asics.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
drivers/gpu/drm/amd/amdgpu/si_dma.c

index 8c36765d3f028d34067784bf3e0744f4047bfa63..2541d7013e03782e14341b4d149456bb0b8babbe 100644 (file)
@@ -280,7 +280,7 @@ struct amdgpu_vm_pte_funcs {
        void (*set_pte_pde)(struct amdgpu_ib *ib,
                            uint64_t pe,
                            uint64_t addr, unsigned count,
-                           uint32_t incr, uint32_t flags);
+                           uint32_t incr, uint64_t flags);
 };
 
 /* provided by the gmc block */
@@ -293,7 +293,7 @@ struct amdgpu_gart_funcs {
                           void *cpu_pt_addr, /* cpu addr of page table */
                           uint32_t gpu_page_idx, /* pte/pde to update */
                           uint64_t addr, /* addr to write into pte/pde */
-                          uint32_t flags); /* access flags */
+                          uint64_t flags); /* access flags */
        /* enable/disable PRT support */
        void (*set_prt)(struct amdgpu_device *adev, bool enable);
 };
@@ -539,7 +539,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
                        int pages);
 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
                     int pages, struct page **pagelist,
-                    dma_addr_t *dma_addr, uint32_t flags);
+                    dma_addr_t *dma_addr, uint64_t flags);
 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
 
 /*
@@ -1746,7 +1746,7 @@ bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
                                       int *last_invalidated);
 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
-uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
+uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
                                 struct ttm_mem_reg *mem);
 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
index 964d2a946ed5514278f09642cbec0bf3439724d4..2916fabf3d1b9dca0c86b1df0a3c104add3011a0 100644 (file)
@@ -229,7 +229,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
        unsigned p;
        int i, j;
        u64 page_base;
-       uint32_t flags = AMDGPU_PTE_SYSTEM;
+       uint64_t flags = AMDGPU_PTE_SYSTEM;
 
        if (!adev->gart.ready) {
                WARN(1, "trying to unbind memory from uninitialized GART !\n");
@@ -271,7 +271,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
  */
 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
                     int pages, struct page **pagelist, dma_addr_t *dma_addr,
-                    uint32_t flags)
+                    uint64_t flags)
 {
        unsigned t;
        unsigned p;
index 4c6094eefc51ccd638cf7f73759cd1f4d55e95e5..f2241bb679878acd2ef899b105f580c5fc2af595 100644 (file)
@@ -746,7 +746,7 @@ int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
 {
        struct ttm_tt *ttm = bo->ttm;
        struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
-       uint32_t flags;
+       uint64_t flags;
        int r;
 
        if (!ttm || amdgpu_ttm_is_bound(ttm))
@@ -1027,10 +1027,10 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
        return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 }
 
-uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
+uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
                                 struct ttm_mem_reg *mem)
 {
-       uint32_t flags = 0;
+       uint64_t flags = 0;
 
        if (mem && mem->mem_type != TTM_PL_SYSTEM)
                flags |= AMDGPU_PTE_VALID;
index 7e22c3558b296600e243cf445c9426577352aa2d..a45de6e6a0f73af16700687e9a42833a0dfb628c 100644 (file)
@@ -64,7 +64,7 @@ struct amdgpu_pte_update_params {
        /* Function which actually does the update */
        void (*func)(struct amdgpu_pte_update_params *params, uint64_t pe,
                     uint64_t addr, unsigned count, uint32_t incr,
-                    uint32_t flags);
+                    uint64_t flags);
        /* indicate update pt or its shadow */
        bool shadow;
 };
@@ -496,7 +496,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
                                  uint64_t pe, uint64_t addr,
                                  unsigned count, uint32_t incr,
-                                 uint32_t flags)
+                                 uint64_t flags)
 {
        trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
 
@@ -525,7 +525,7 @@ static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
                                   uint64_t pe, uint64_t addr,
                                   unsigned count, uint32_t incr,
-                                  uint32_t flags)
+                                  uint64_t flags)
 {
        uint64_t src = (params->src + (addr >> 12) * 8);
 
@@ -718,7 +718,7 @@ error_free:
 static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
                                  struct amdgpu_vm *vm,
                                  uint64_t start, uint64_t end,
-                                 uint64_t dst, uint32_t flags)
+                                 uint64_t dst, uint64_t flags)
 {
        const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
 
@@ -808,7 +808,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
 static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params        *params,
                                struct amdgpu_vm *vm,
                                uint64_t start, uint64_t end,
-                               uint64_t dst, uint32_t flags)
+                               uint64_t dst, uint64_t flags)
 {
        /**
         * The MC L1 TLB supports variable sized pages, based on a fragment
@@ -885,7 +885,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
                                       dma_addr_t *pages_addr,
                                       struct amdgpu_vm *vm,
                                       uint64_t start, uint64_t last,
-                                      uint32_t flags, uint64_t addr,
+                                      uint64_t flags, uint64_t addr,
                                       struct dma_fence **fence)
 {
        struct amdgpu_ring *ring;
@@ -1023,11 +1023,11 @@ error_free:
  */
 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
                                      struct dma_fence *exclusive,
-                                     uint32_t gtt_flags,
+                                     uint64_t gtt_flags,
                                      dma_addr_t *pages_addr,
                                      struct amdgpu_vm *vm,
                                      struct amdgpu_bo_va_mapping *mapping,
-                                     uint32_t flags,
+                                     uint64_t flags,
                                      struct drm_mm_node *nodes,
                                      struct dma_fence **fence)
 {
@@ -1114,7 +1114,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
        struct amdgpu_vm *vm = bo_va->vm;
        struct amdgpu_bo_va_mapping *mapping;
        dma_addr_t *pages_addr = NULL;
-       uint32_t gtt_flags, flags;
+       uint64_t gtt_flags, flags;
        struct ttm_mem_reg *mem;
        struct drm_mm_node *nodes;
        struct dma_fence *exclusive;
index 3eee569701d7febb1a344884df14eb7b3be3644d..0b62764caa283a5d62d8cd7ca341edca7be36c73 100644 (file)
@@ -749,7 +749,7 @@ static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
  */
 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
                                    uint64_t addr, unsigned count,
-                                   uint32_t incr, uint32_t flags)
+                                   uint32_t incr, uint64_t flags)
 {
        /* for physically contiguous pages (vram) */
        ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
index d3b7fe88452c325d28a72fede751081df157ed9f..c3c6853051cd2a50891ea1129f683a5794102ee3 100644 (file)
@@ -367,7 +367,7 @@ static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev,
                                     void *cpu_pt_addr,
                                     uint32_t gpu_page_idx,
                                     uint64_t addr,
-                                    uint32_t flags)
+                                    uint64_t flags)
 {
        void __iomem *ptr = (void *)cpu_pt_addr;
        uint64_t value;
index 9f761e4e03db47324ddd9d0ba93f9f52cf2744c0..e95af8ae0ac84914e9415022a459b10bdf07fb8d 100644 (file)
@@ -439,7 +439,7 @@ static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
                                     void *cpu_pt_addr,
                                     uint32_t gpu_page_idx,
                                     uint64_t addr,
-                                    uint32_t flags)
+                                    uint64_t flags)
 {
        void __iomem *ptr = (void *)cpu_pt_addr;
        uint64_t value;
index 724ec3745c8cb73400c054ef804c5b55d0bc50a5..17d19f06ce4a0838d73799a7505c8b13e7ed3571 100644 (file)
@@ -531,7 +531,7 @@ static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
                                     void *cpu_pt_addr,
                                     uint32_t gpu_page_idx,
                                     uint64_t addr,
-                                    uint32_t flags)
+                                    uint64_t flags)
 {
        void __iomem *ptr = (void *)cpu_pt_addr;
        uint64_t value;
index 0b1aa946260845fdb1ac782955e416cf4e84e1e5..1a4b351f350b4fc1e2904fda3136257a183c1187 100644 (file)
@@ -798,7 +798,7 @@ static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
  */
 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
                                     uint64_t addr, unsigned count,
-                                    uint32_t incr, uint32_t flags)
+                                    uint32_t incr, uint64_t flags)
 {
        /* for physically contiguous pages (vram) */
        ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
index 610bc3e4a72868cb56718e9ac5eb3b48c742d232..49a099aa9c885abaa3c21ddff82dbe8c29134507 100644 (file)
@@ -1007,7 +1007,7 @@ static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
  */
 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
                                     uint64_t addr, unsigned count,
-                                    uint32_t incr, uint32_t flags)
+                                    uint32_t incr, uint64_t flags)
 {
        /* for physically contiguous pages (vram) */
        ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
index d2edd3212344dcc121135dcda656b7ff745ab40c..a6862b185bbf030e69de2fcea00aae0a3f3a09e5 100644 (file)
@@ -398,7 +398,7 @@ static void si_dma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib,
                                     uint64_t pe,
                                     uint64_t addr, unsigned count,
-                                    uint32_t incr, uint32_t flags)
+                                    uint32_t incr, uint64_t flags)
 {
        uint64_t value;
        unsigned ndw;