clk: fractional-divider: support for divider bypassing

If the divider or multiplier values are 0 in the register, bypassing the
divider and returning the parent clock rate in clk_fd_recalc_rate().

Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed commitlog typo]

diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index 82a59d0086cc79d654c4ceaf4aa42a8491467dbc..6aa72d9d79bad43d5c8f79f47fa30134d710a624 100644 (file)
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -36,6 +36,9 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
        m = (val & fd->mmask) >> fd->mshift;
        n = (val & fd->nmask) >> fd->nshift;
 
+       if (!n || !m)
+               return parent_rate;
+
        ret = (u64)parent_rate * m;
        do_div(ret, n);