Convert the omap2plus platforms to be using CONFIG_MULTI_IRQ_HANDLER.
Each machine is modified to provide either omap2_intc_handle_irq(),
omap3_intc_handle_irq() or gic_handle_irq().
This allows for a major cleanup, removing the MULTI_OMAP setup
from the interrupt path.
Tested on both Panda and IGEPv2 (single kernel image)
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
depends on ARCH_OMAP2PLUS
default y
select CPU_V6
+ select MULTI_IRQ_HANDLER
config ARCH_OMAP3
bool "TI OMAP3"
.map_io = omap243x_map_io,
.init_early = omap2430_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = omap_2430sdp_init,
.timer = &omap2_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap_3430sdp_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap3630_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap_sdp_init,
.timer = &omap3_timer,
MACHINE_END
#include <mach/hardware.h>
#include <mach/omap4-common.h>
+#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
.map_io = omap4_map_io,
.init_early = omap4430_init_early,
.init_irq = gic_init_irq,
+ .handle_irq = gic_handle_irq,
.init_machine = omap_4430sdp_init,
.timer = &omap4_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = am35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = am3517_crane_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = am35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = am3517_evm_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = omap_apollon_init,
.timer = &omap2_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = cm_t35_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap3630_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = cm_t3730_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = am35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = cm_t3517_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = devkit8000_init,
.timer = &omap3_secure_timer,
MACHINE_END
.map_io = omap243x_map_io,
.init_early = omap2430_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = omap_generic_init,
.timer = &omap2_timer,
.dt_compat = omap243x_boards_compat,
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = omap_h4_init,
.timer = &omap2_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = igep_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = igep_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap_ldp_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.timer = &omap2_timer,
MACHINE_END
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.timer = &omap2_timer,
MACHINE_END
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_irq = omap2_init_irq,
+ .handle_irq = omap2_intc_handle_irq,
.init_machine = n8x0_init_machine,
.timer = &omap2_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap3_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_beagle_init,
.timer = &omap3_secure_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_evm_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3logic_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3logic_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3pandora_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_stalker_init,
.timer = &omap3_secure_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap3_touchbook_init,
.timer = &omap3_secure_timer,
MACHINE_END
#include <mach/hardware.h>
#include <mach/omap4-common.h>
+#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
.map_io = omap4_map_io,
.init_early = omap4430_init_early,
.init_irq = gic_init_irq,
+ .handle_irq = gic_handle_irq,
.init_machine = omap4_panda_init,
.timer = &omap4_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap35xx_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = overo_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap3630_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = rm680_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = rx51_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap_zoom_init,
.timer = &omap3_timer,
MACHINE_END
.map_io = omap3_map_io,
.init_early = omap3630_init_early,
.init_irq = omap3_init_irq,
+ .handle_irq = omap3_intc_handle_irq,
.init_machine = omap_zoom_init,
.timer = &omap3_timer,
MACHINE_END
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/irqs.h>
-#include <asm/hardware/gic.h>
-
-#include <plat/omap24xx.h>
-#include <plat/omap34xx.h>
-#include <plat/omap44xx.h>
-
-#include <plat/multi.h>
-
-#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
-#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
-#define OMAP4_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
-#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
-#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
.macro disable_fiq
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
-
-/*
- * Unoptimized irq functions for multi-omap2, 3 and 4
- */
-
-#ifdef MULTI_OMAP2
- /*
- * Configure the interrupt base on the first interrupt.
- * See also omap_irq_base_init for setting omap_irq_base.
- */
- .macro get_irqnr_preamble, base, tmp
- ldr \base, =omap_irq_base @ irq base address
- ldr \base, [\base, #0] @ irq base value
- .endm
-
- /* Check the pending interrupts. Note that base already set */
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- tst \base, #0x100 @ gic address?
- bne 4401f @ found gic
-
- /* Handle omap2 and omap3 */
- ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
- cmp \irqnr, #0x0
- bne 9998f
- ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
- cmp \irqnr, #0x0
- bne 9998f
- ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
- cmp \irqnr, #0x0
- bne 9998f
-
- /*
- * ti816x has additional IRQ pending register. Checking this
- * register on omap2 & omap3 has no effect (read as 0).
- */
- ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
- cmp \irqnr, #0x0
-9998:
- ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
- and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
- b 9999f
-
- /* Handle omap4 */
-4401: ldr \irqstat, [\base, #GIC_CPU_INTACK]
- ldr \tmp, =1021
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #15
- cmpcc \irqnr, \irqnr
- cmpne \irqnr, \tmp
- cmpcs \irqnr, \irqnr
-9999:
- .endm
-
-#ifdef CONFIG_SMP
- /* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt
- * on the controller, since this requires the original irqstat
- * value which we won't easily be able to recreate later.
- */
-
- .macro test_for_ipi, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- cmp \irqnr, #16
- it cc
- strcc \irqstat, [\base, #GIC_CPU_EOI]
- it cs
- cmpcs \irqnr, \irqnr
- .endm
-#endif /* CONFIG_SMP */
-
-#else /* MULTI_OMAP2 */
-
-
-/*
- * Optimized irq functions for omap2, 3 and 4
- */
-
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
- .macro get_irqnr_preamble, base, tmp
-#ifdef CONFIG_ARCH_OMAP2
- ldr \base, =OMAP2_IRQ_BASE
-#else
- ldr \base, =OMAP3_IRQ_BASE
-#endif
- .endm
-
- /* Check the pending interrupts. Note that base already set */
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
- cmp \irqnr, #0x0
- bne 9999f
- ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
- cmp \irqnr, #0x0
- bne 9999f
- ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
- cmp \irqnr, #0x0
-#ifdef CONFIG_SOC_OMAPTI816X
- bne 9999f
- ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
- cmp \irqnr, #0x0
-#endif
-9999:
- ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
- and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
-
- .endm
-#endif
-
-
-#ifdef CONFIG_ARCH_OMAP4
-#define HAVE_GET_IRQNR_PREAMBLE
-#include <asm/hardware/entry-macro-gic.S>
-
- .macro get_irqnr_preamble, base, tmp
- ldr \base, =OMAP4_IRQ_BASE
- .endm
-
-#endif
-
-#endif /* MULTI_OMAP2 */
select CLKDEV_LOOKUP
select GENERIC_IRQ_CHIP
select OMAP_DM_TIMER
+ select MULTI_IRQ_HANDLER
help
"Systems based on OMAP2, OMAP3 or OMAP4"