--- /dev/null
+/*
+ * Common Blackfin IRQ definitions (i.e. the CEC)
+ *
+ * Copyright 2005-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _MACH_COMMON_IRQ_H_
+#define _MACH_COMMON_IRQ_H_
+
+/*
+ * Core events interrupt source definitions
+ *
+ * Event Source Event Name
+ * Emulation EMU 0 (highest priority)
+ * Reset RST 1
+ * NMI NMI 2
+ * Exception EVX 3
+ * Reserved -- 4
+ * Hardware Error IVHW 5
+ * Core Timer IVTMR 6
+ * Peripherals IVG7 7
+ * Peripherals IVG8 8
+ * Peripherals IVG9 9
+ * Peripherals IVG10 10
+ * Peripherals IVG11 11
+ * Peripherals IVG12 12
+ * Peripherals IVG13 13
+ * Softirq IVG14 14
+ * System Call IVG15 15 (lowest priority)
+ */
+
+/* The ABSTRACT IRQ definitions */
+#define IRQ_EMU 0 /* Emulation */
+#define IRQ_RST 1 /* reset */
+#define IRQ_NMI 2 /* Non Maskable */
+#define IRQ_EVX 3 /* Exception */
+#define IRQ_UNUSED 4 /* - unused interrupt */
+#define IRQ_HWERR 5 /* Hardware Error */
+#define IRQ_CORETMR 6 /* Core timer */
+
+#define BFIN_IRQ(x) ((x) + 7)
+
+#define IVG7 7
+#define IVG8 8
+#define IVG9 9
+#define IVG10 10
+#define IVG11 11
+#define IVG12 12
+#define IVG13 13
+#define IVG14 14
+#define IVG15 15
+
+#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
+
+#endif
#ifndef _BF518_IRQ_H_
#define _BF518_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
- Core Emulation **
- Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
-
- .....
-
- Software Interrupt 1 IVG14 31
- Software Interrupt 2 --
- (lowest priority) IVG15 32 *
-*/
+#include <mach-common/irq.h>
#define NR_PERI_INTS (2 * 32)
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define BFIN_IRQ(x) ((x) + 7)
-
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
#ifndef _BF527_IRQ_H_
#define _BF527_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
- Core Emulation **
- Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
-
- .....
-
- Software Interrupt 1 IVG14 31
- Software Interrupt 2 --
- (lowest priority) IVG15 32 *
-*/
+#include <mach-common/irq.h>
#define NR_PERI_INTS (2 * 32)
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define BFIN_IRQ(x) ((x) + 7)
-
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
#ifndef _BF533_IRQ_H_
#define _BF533_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
-Core Emulation **
- Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
- PLL Wakeup Interrupt IVG7 7
- DMA Error (generic) IVG7 8
- PPI Error Interrupt IVG7 9
- SPORT0 Error Interrupt IVG7 10
- SPORT1 Error Interrupt IVG7 11
- SPI Error Interrupt IVG7 12
- UART Error Interrupt IVG7 13
- RTC Interrupt IVG8 14
- DMA0 Interrupt (PPI) IVG8 15
- DMA1 (SPORT0 RX) IVG9 16
- DMA2 (SPORT0 TX) IVG9 17
- DMA3 (SPORT1 RX) IVG9 18
- DMA4 (SPORT1 TX) IVG9 19
- DMA5 (PPI) IVG10 20
- DMA6 (UART RX) IVG10 21
- DMA7 (UART TX) IVG10 22
- Timer0 IVG11 23
- Timer1 IVG11 24
- Timer2 IVG11 25
- PF Interrupt A IVG12 26
- PF Interrupt B IVG12 27
- DMA8/9 Interrupt IVG13 28
- DMA10/11 Interrupt IVG13 29
- Watchdog Timer IVG13 30
+#include <mach-common/irq.h>
- Softirq IVG14 31
- System Call --
- (lowest priority) IVG15 32 *
- */
#define SYS_IRQS 31
#define NR_PERI_INTS 24
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /*Emulation */
-#define IRQ_RST 1 /*reset */
-#define IRQ_NMI 2 /*Non Maskable */
-#define IRQ_EVX 3 /*Exception */
-#define IRQ_UNUSED 4 /*- unused interrupt*/
-#define IRQ_HWERR 5 /*Hardware Error */
-#define IRQ_CORETMR 6 /*Core timer */
-
#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_MACH_IRQS (IRQ_PF15 + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
/* IAR0 BIT FIELDS*/
#define RTC_ERROR_POS 28
#ifndef _BF537_IRQ_H_
#define _BF537_IRQ_H_
-/*
- * Interrupt source definitions
- * Event Source Core Event Name
- * Core Emulation **
- * Events (highest priority) EMU 0
- * Reset RST 1
- * NMI NMI 2
- * Exception EVX 3
- * Reserved -- 4
- * Hardware Error IVHW 5
- * Core Timer IVTMR 6
- * .....
- *
- * Softirq IVG14
- * System Call --
- * (lowest priority) IVG15
- */
+#include <mach-common/irq.h>
#define SYS_IRQS 39
#define NR_PERI_INTS 32
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /*Emulation */
-#define IRQ_RST 1 /*reset */
-#define IRQ_NMI 2 /*Non Maskable */
-#define IRQ_EVX 3 /*Exception */
-#define IRQ_UNUSED 4 /*- unused interrupt*/
-#define IRQ_HWERR 5 /*Hardware Error */
-#define IRQ_CORETMR 6 /*Core timer */
-
#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */
#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
/* IAR0 BIT FIELDS*/
#define IRQ_PLL_WAKEUP_POS 0
#ifndef _BF538_IRQ_H_
#define _BF538_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
- Core Emulation **
- Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
-
- .....
-
- Software Interrupt 1 IVG14 31
- Software Interrupt 2 --
- (lowest priority) IVG15 32 *
-*/
+#include <mach-common/irq.h>
#define NR_PERI_INTS (2 * 32)
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define BFIN_IRQ(x) ((x) + 7)
-
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_MACH_IRQS (IRQ_PF15 + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
#ifndef _BF548_IRQ_H_
#define _BF548_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
-Core Emulation **
-Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
-
-.....
-
- Software Interrupt 1 IVG14 31
- Software Interrupt 2 --
- (lowest priority) IVG15 32 *
- */
+#include <mach-common/irq.h>
#define NR_PERI_INTS (32 * 3)
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt*/
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define BFIN_IRQ(x) ((x) + 7)
-
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */
#define GPIO_IRQ_BASE IRQ_PA0
#define NR_MACH_IRQS (IRQ_PJ15 + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
/* For compatibility reasons with existing code */
#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
-
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
#define IRQ_DMAC0_ERR_POS 4
#ifndef _BF561_IRQ_H_
#define _BF561_IRQ_H_
-/***********************************************************************
- * Interrupt source definitions:
- Event Source Core Event Name IRQ No
- (highest priority)
- Emulation Events EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
-
- PLL Wakeup Interrupt IVG7 7
- DMA1 Error (generic) IVG7 8
- DMA2 Error (generic) IVG7 9
- IMDMA Error (generic) IVG7 10
- PPI1 Error Interrupt IVG7 11
- PPI2 Error Interrupt IVG7 12
- SPORT0 Error Interrupt IVG7 13
- SPORT1 Error Interrupt IVG7 14
- SPI Error Interrupt IVG7 15
- UART Error Interrupt IVG7 16
- Reserved Interrupt IVG7 17
-
- DMA1 0 Interrupt(PPI1) IVG8 18
- DMA1 1 Interrupt(PPI2) IVG8 19
- DMA1 2 Interrupt IVG8 20
- DMA1 3 Interrupt IVG8 21
- DMA1 4 Interrupt IVG8 22
- DMA1 5 Interrupt IVG8 23
- DMA1 6 Interrupt IVG8 24
- DMA1 7 Interrupt IVG8 25
- DMA1 8 Interrupt IVG8 26
- DMA1 9 Interrupt IVG8 27
- DMA1 10 Interrupt IVG8 28
- DMA1 11 Interrupt IVG8 29
-
- DMA2 0 (SPORT0 RX) IVG9 30
- DMA2 1 (SPORT0 TX) IVG9 31
- DMA2 2 (SPORT1 RX) IVG9 32
- DMA2 3 (SPORT2 TX) IVG9 33
- DMA2 4 (SPI) IVG9 34
- DMA2 5 (UART RX) IVG9 35
- DMA2 6 (UART TX) IVG9 36
- DMA2 7 Interrupt IVG9 37
- DMA2 8 Interrupt IVG9 38
- DMA2 9 Interrupt IVG9 39
- DMA2 10 Interrupt IVG9 40
- DMA2 11 Interrupt IVG9 41
-
- TIMER 0 Interrupt IVG10 42
- TIMER 1 Interrupt IVG10 43
- TIMER 2 Interrupt IVG10 44
- TIMER 3 Interrupt IVG10 45
- TIMER 4 Interrupt IVG10 46
- TIMER 5 Interrupt IVG10 47
- TIMER 6 Interrupt IVG10 48
- TIMER 7 Interrupt IVG10 49
- TIMER 8 Interrupt IVG10 50
- TIMER 9 Interrupt IVG10 51
- TIMER 10 Interrupt IVG10 52
- TIMER 11 Interrupt IVG10 53
-
- Programmable Flags0 A (8) IVG11 54
- Programmable Flags0 B (8) IVG11 55
- Programmable Flags1 A (8) IVG11 56
- Programmable Flags1 B (8) IVG11 57
- Programmable Flags2 A (8) IVG11 58
- Programmable Flags2 B (8) IVG11 59
-
- MDMA1 0 write/read INT IVG8 60
- MDMA1 1 write/read INT IVG8 61
-
- MDMA2 0 write/read INT IVG9 62
- MDMA2 1 write/read INT IVG9 63
-
- IMDMA 0 write/read INT IVG12 64
- IMDMA 1 write/read INT IVG12 65
-
- Watch Dog Timer IVG13 66
-
- Reserved interrupt IVG7 67
- Reserved interrupt IVG7 68
- Supplemental interrupt 0 IVG7 69
- supplemental interrupt 1 IVG7 70
-
- Softirq IVG14
- System Call --
- (lowest priority) IVG15
-
- **********************************************************************/
+#include <mach-common/irq.h>
#define SYS_IRQS 71
#define NR_PERI_INTS 64
-/*
- * The ABSTRACT IRQ definitions
- * the first seven of the following are fixed,
- * the rest you change if you need to.
- */
-/* IVG 0-6*/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* Reset */
-#define IRQ_NMI 2 /* Non Maskable Interrupt */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* Reserved interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
#define IVG_BASE 7
/* IVG 7 */
#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_MACH_IRQS (IRQ_PF47 + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
/*
* DEFAULT PRIORITIES:
projects / GitHub / exynos8895 / android_kernel_samsung_universal8895.git / commitdiff