int __init init_cyclone_clock(void)
{
- u64* reg;
+ u64 __iomem *reg;
u64 base; /* saved cyclone base address */
u64 offset; /* offset from pageaddr to cyclone_timer register */
int i;
- u32* volatile cyclone_timer; /* Cyclone MPMC0 register */
+ u32 __iomem *cyclone_timer; /* Cyclone MPMC0 register */
if (!use_cyclone)
return 0;
/* find base address */
offset = (CYCLONE_CBAR_ADDR);
- reg = (u64*)ioremap_nocache(offset, sizeof(u64));
+ reg = ioremap_nocache(offset, sizeof(u64));
if(!reg){
printk(KERN_ERR "Summit chipset: Could not find valid CBAR"
" register.\n");
/* setup PMCC */
offset = (base + CYCLONE_PMCC_OFFSET);
- reg = (u64*)ioremap_nocache(offset, sizeof(u64));
+ reg = ioremap_nocache(offset, sizeof(u64));
if(!reg){
printk(KERN_ERR "Summit chipset: Could not find valid PMCC"
" register.\n");
/* setup MPCS */
offset = (base + CYCLONE_MPCS_OFFSET);
- reg = (u64*)ioremap_nocache(offset, sizeof(u64));
+ reg = ioremap_nocache(offset, sizeof(u64));
if(!reg){
printk(KERN_ERR "Summit chipset: Could not find valid MPCS"
" register.\n");
/* map in cyclone_timer */
offset = (base + CYCLONE_MPMC_OFFSET);
- cyclone_timer = (u32*)ioremap_nocache(offset, sizeof(u32));
+ cyclone_timer = ioremap_nocache(offset, sizeof(u32));
if(!cyclone_timer){
printk(KERN_ERR "Summit chipset: Could not find valid MPMC"
" register.\n");
printk(KERN_ERR "Summit chipset: Counter not counting!"
" DISABLED\n");
iounmap(cyclone_timer);
- cyclone_timer = 0;
+ cyclone_timer = NULL;
use_cyclone = 0;
return -ENODEV;
}