#include "mphy.h"
#include "ufs-exynos.h"
-#if defined(CONFIG_SOC_EXYNOS9610)
static struct exynos_ufs_sfr_log ufs_log_sfr[] = {
{"STD HCI SFR" , LOG_STD_HCI_SFR, 0},
{"UIC COMMAND ARG3" , REG_UIC_COMMAND_ARG_3, 0},
{"CCAP" , REG_CRYPTO_CAPABILITY, 0},
-
{"VS HCI SFR" , LOG_VS_HCI_SFR, 0},
{"TXPRDT ENTRY SIZE" , HCI_TXPRDT_ENTRY_SIZE, 0},
{"PMA SFR" , LOG_PMA_SFR, 0},
+ {"COMN 0x2f", (0x00BC), 0},
+ {"TRSV_L0 0x4b", (0x01EC), 0},
+ {"TRSV_L0 0x4f", (0x01FC), 0},
+ {"TRSV_L1 0x4b", (0x032C), 0},
+ {"TRSV_L1 0x4f", (0x033C), 0},
{"0x74", 0x74, 0},
{"0x110", 0x110, 0},
{"0x134", 0x134, 0},
{"0xE0", 0xE0, 0},
{"0x164", 0x164, 0},
{"0x8C", 0x8C, 0},
-
- {"0xC8", 0xC8, 0},
- {"0xF0", 0xF0, 0},
- {"0x120",0x120, 0},
+ {"0xC8", 0xC8, 0},
+ {"0xF0", 0xF0, 0},
+ {"0x120", 0x120, 0},
{},
};
{UIC_ARG_MIB(0x15C1), 0, 0},
/* PA Debug */
-
+ {UIC_ARG_MIB(0x9514), 0, 0},
+ {UIC_ARG_MIB(0x9536), 0, 0},
+ {UIC_ARG_MIB(0x9556), 0, 0},
+ {UIC_ARG_MIB(0x9564), 0, 0},
+ {UIC_ARG_MIB(0x9566), 0, 0},
+ {UIC_ARG_MIB(0x9567), 0, 0},
+ {UIC_ARG_MIB(0x9568), 0, 0},
+ {UIC_ARG_MIB(0x956A), 0, 0},
+ {UIC_ARG_MIB(0x9595), 0, 0},
+ {UIC_ARG_MIB(0x9596), 0, 0},
+ {UIC_ARG_MIB(0x9597), 0, 0},
/* DL Standard */
{UIC_ARG_MIB(0x2046), 0, 0},
{UIC_ARG_MIB(0x2047), 0, 0},
{UIC_ARG_MIB(0x2067), 0, 0},
/* DL Debug */
-
+ {UIC_ARG_MIB(0xA000), 0, 0},
+ {UIC_ARG_MIB(0xA005), 0, 0},
+ {UIC_ARG_MIB(0xA007), 0, 0},
+ {UIC_ARG_MIB(0xA010), 0, 0},
+ {UIC_ARG_MIB(0xA011), 0, 0},
+ {UIC_ARG_MIB(0xA020), 0, 0},
+ {UIC_ARG_MIB(0xA021), 0, 0},
+ {UIC_ARG_MIB(0xA022), 0, 0},
+ {UIC_ARG_MIB(0xA023), 0, 0},
+ {UIC_ARG_MIB(0xA024), 0, 0},
+ {UIC_ARG_MIB(0xA025), 0, 0},
+ {UIC_ARG_MIB(0xA026), 0, 0},
+ {UIC_ARG_MIB(0xA027), 0, 0},
+ {UIC_ARG_MIB(0xA028), 0, 0},
+ {UIC_ARG_MIB(0xA029), 0, 0},
+ {UIC_ARG_MIB(0xA02A), 0, 0},
+ {UIC_ARG_MIB(0xA02B), 0, 0},
+ {UIC_ARG_MIB(0xA100), 0, 0},
+ {UIC_ARG_MIB(0xA101), 0, 0},
+ {UIC_ARG_MIB(0xA102), 0, 0},
+ {UIC_ARG_MIB(0xA103), 0, 0},
+ {UIC_ARG_MIB(0xA114), 0, 0},
+ {UIC_ARG_MIB(0xA115), 0, 0},
+ {UIC_ARG_MIB(0xA116), 0, 0},
+ {UIC_ARG_MIB(0xA120), 0, 0},
+ {UIC_ARG_MIB(0xA121), 0, 0},
+ {UIC_ARG_MIB(0xA122), 0, 0},
/* NL Standard */
{UIC_ARG_MIB(0x3000), 0, 0},
{UIC_ARG_MIB(0x3001), 0, 0},
/* NL Debug */
-
+ {UIC_ARG_MIB(0xB010), 0, 0},
+ {UIC_ARG_MIB(0xB011), 0, 0},
/* TL Standard */
{UIC_ARG_MIB(0x4020), 0, 0},
{UIC_ARG_MIB(0x4021), 0, 0},
{UIC_ARG_MIB(0x402B), 0, 0},
/* TL Debug */
-
- /* MPHY PCS Lane 0 Standard*/
- {UIC_ARG_MIB_SEL(0x0004, TX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB(0xC001), 0, 0},
+ {UIC_ARG_MIB(0xC024), 0, 0},
+ {UIC_ARG_MIB(0xC025), 0, 0},
+ {UIC_ARG_MIB(0xC026), 0, 0},
+ /* MPHY PCS Lane 0*/
{UIC_ARG_MIB_SEL(0x0021, TX_LANE_0+0), 0, 0},
{UIC_ARG_MIB_SEL(0x0022, TX_LANE_0+0), 0, 0},
{UIC_ARG_MIB_SEL(0x0023, TX_LANE_0+0), 0, 0},
};
static struct exynos_ufs_sfr_log ufs_show_sfr[] = {
- {},
-};
-
-static struct exynos_ufs_attr_log ufs_show_attr[] = {
- {},
-};
-#elif defined(CONFIG_SOC_EXYNOS9810)
-/*
- * This is a list for latest SoC.
- */
-static struct exynos_ufs_sfr_log ufs_log_sfr[] = {
{"STD HCI SFR" , LOG_STD_HCI_SFR, 0},
{"INTERRUPT STATUS" , REG_INTERRUPT_STATUS, 0},
{"INTERRUPT ENABLE" , REG_INTERRUPT_ENABLE, 0},
{"CONTROLLER STATUS" , REG_CONTROLLER_STATUS, 0},
{"CONTROLLER ENABLE" , REG_CONTROLLER_ENABLE, 0},
+ {"UIC ERR PHY ADAPTER LAYER" , REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER, 0},
+ {"UIC ERR DATA LINK LAYER" , REG_UIC_ERROR_CODE_DATA_LINK_LAYER, 0},
+ {"UIC ERR NETWORK LATER" , REG_UIC_ERROR_CODE_NETWORK_LAYER, 0},
+ {"UIC ERR TRANSPORT LAYER" , REG_UIC_ERROR_CODE_TRANSPORT_LAYER, 0},
+ {"UIC ERR DME" , REG_UIC_ERROR_CODE_DME, 0},
{"UTP TRANSF REQ INT AGG CNTRL" , REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL, 0},
{"UTP TRANSF REQ LIST BASE L" , REG_UTP_TRANSFER_REQ_LIST_BASE_L, 0},
{"UTP TRANSF REQ LIST BASE H" , REG_UTP_TRANSFER_REQ_LIST_BASE_H, 0},
{"UIC COMMAND ARG3" , REG_UIC_COMMAND_ARG_3, 0},
{"CCAP" , REG_CRYPTO_CAPABILITY, 0},
-
{"VS HCI SFR" , LOG_VS_HCI_SFR, 0},
{"TXPRDT ENTRY SIZE" , HCI_TXPRDT_ENTRY_SIZE, 0},
{"PMA SFR" , LOG_PMA_SFR, 0},
- {"COMN 0x2f" , (0x00BC), 0},
- {"TRSV_L0 0x4b" , (0x01EC), 0},
- {"TRSV_L0 0x4f" , (0x01FC), 0},
- {"TRSV_L1 0x4b" , (0x032C), 0},
- {"TRSV_L1 0x4f" , (0x033C), 0},
-
+ {"COMN 0x2f", (0x00BC), 0},
+ {"TRSV_L0 0x4b", (0x01EC), 0},
+ {"TRSV_L0 0x4f", (0x01FC), 0},
+ {"TRSV_L1 0x4b", (0x032C), 0},
+ {"TRSV_L1 0x4f", (0x033C), 0},
+ {"0x74", 0x74, 0},
+ {"0x110", 0x110, 0},
+ {"0x134", 0x134, 0},
+ {"0x16C", 0x16C, 0},
+ {"0x178", 0x178, 0},
+ {"0x1B0", 0x1B0, 0},
+ {"0xE0", 0xE0, 0},
+ {"0x164", 0x164, 0},
+ {"0x8C", 0x8C, 0},
+ {"0xC8", 0xC8, 0},
+ {"0xF0", 0xF0, 0},
+ {"0x120", 0x120, 0},
{},
};
-static struct exynos_ufs_attr_log ufs_log_attr[] = {
+static struct exynos_ufs_attr_log ufs_show_attr[] = {
/* PA Standard */
{UIC_ARG_MIB(0x1520), 0, 0},
{UIC_ARG_MIB(0x1540), 0, 0},
{UIC_ARG_MIB(0x15A8), 0, 0},
{UIC_ARG_MIB(0x15C0), 0, 0},
{UIC_ARG_MIB(0x15C1), 0, 0},
+
/* PA Debug */
{UIC_ARG_MIB(0x9514), 0, 0},
{UIC_ARG_MIB(0x9536), 0, 0},
{UIC_ARG_MIB(0x2047), 0, 0},
{UIC_ARG_MIB(0x2066), 0, 0},
{UIC_ARG_MIB(0x2067), 0, 0},
+
/* DL Debug */
{UIC_ARG_MIB(0xA000), 0, 0},
{UIC_ARG_MIB(0xA005), 0, 0},
/* NL Standard */
{UIC_ARG_MIB(0x3000), 0, 0},
{UIC_ARG_MIB(0x3001), 0, 0},
+
/* NL Debug */
{UIC_ARG_MIB(0xB010), 0, 0},
{UIC_ARG_MIB(0xB011), 0, 0},
{UIC_ARG_MIB(0x4023), 0, 0},
{UIC_ARG_MIB(0x4025), 0, 0},
{UIC_ARG_MIB(0x402B), 0, 0},
+
/* TL Debug */
{UIC_ARG_MIB(0xC001), 0, 0},
{UIC_ARG_MIB(0xC024), 0, 0},
{UIC_ARG_MIB_SEL(0x0035, TX_LANE_0+0), 0, 0},
{UIC_ARG_MIB_SEL(0x0036, TX_LANE_0+0), 0, 0},
{UIC_ARG_MIB_SEL(0x0041, TX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A1, RX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A2, RX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A3, RX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A4, RX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A7, RX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x00C1, RX_LANE_0+0), 0, 0},
- /* MPHY PCS Lane 1*/
- {UIC_ARG_MIB_SEL(0x0021, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0022, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0023, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0024, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0028, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0029, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x002A, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x002B, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x002C, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x002D, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0033, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0035, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0036, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0041, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A1, RX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A2, RX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A3, RX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A4, RX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A7, RX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x00C1, RX_LANE_0+1), 0, 0},
- {},
-};
-
-static struct exynos_ufs_sfr_log ufs_show_sfr[] = {
- {"STD HCI SFR" , LOG_STD_HCI_SFR, 0},
-
- {"INTERRUPT STATUS" , REG_INTERRUPT_STATUS, 0},
- {"CONTROLLER STATUS" , REG_CONTROLLER_STATUS, 0},
- {"UTP TRANSF REQ DOOR BELL" , REG_UTP_TRANSFER_REQ_DOOR_BELL, 0},
- {"UTP TASK REQ DOOR BELL" , REG_UTP_TASK_REQ_DOOR_BELL, 0},
-
- {"VS HCI SFR" , LOG_VS_HCI_SFR, 0},
-
- {"VENDOR SPECIFIC IS" , HCI_VENDOR_SPECIFIC_IS, 0},
- {"RX UPIU MATCH ERROR CODE" , HCI_RX_UPIU_MATCH_ERROR_CODE, 0},
- {"CLKSTOP CTRL", HCI_CLKSTOP_CTRL, 0},
- {"FORCE HCS", HCI_FORCE_HCS, 0},
- {"DMA0 MONITOR STATE" , HCI_DMA0_MONITOR_STATE, 0},
- {"DMA1 MONITOR STATE" , HCI_DMA1_MONITOR_STATE, 0},
- {"SMU ABORT MATCH INFO" , HCI_SMU_ABORT_MATCH_INFO, 0},
-
- {"FMP SFR" , LOG_FMP_SFR, 0},
-
- {"UFSPRSECURITY" , UFSPRSECURITY, 0},
-
-
- {"UNIPRO SFR" , LOG_UNIPRO_SFR, 0},
-
- {"DME_HIBERN8_ENTER_IND_RESULT" , UNIP_DME_HIBERN8_ENTER_IND_RESULT , 0},
- {"DME_HIBERN8_EXIT_IND_RESULT" , UNIP_DME_HIBERN8_EXIT_IND_RESULT , 0},
- {"DME_PWR_IND_RESULT" , UNIP_DME_PWR_IND_RESULT , 0},
- {"DME_DBG_CTRL_FSM" , UNIP_DME_DBG_CTRL_FSM , 0},
-
- {"PMA SFR" , LOG_PMA_SFR, 0},
+ {UIC_ARG_MIB(0x8F), 0, 0},
- {"COMN 0x2f" , (0x00BC), 0},
- {"TRSV_L0 0x4b" , (0x01EC), 0},
- {"TRSV_L0 0x4f" , (0x01FC), 0},
- {"TRSV_L1 0x4b" , (0x032C), 0},
- {"TRSV_L1 0x4f" , (0x033C), 0},
- {},
-};
+ {UIC_ARG_MIB_SEL(0x0F, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x65, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x69, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x21, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x22, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x84, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x35, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x73, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x41, RX_LANE_0+0), 0, 0},
+ {UIC_ARG_MIB_SEL(0x42, RX_LANE_0+0), 0, 0},
-static struct exynos_ufs_attr_log ufs_show_attr[] = {
- /* PA Standard */
- {UIC_ARG_MIB(0x1560), 0, 0},
- {UIC_ARG_MIB(0x1571), 0, 0},
- {UIC_ARG_MIB(0x1580), 0, 0},
- /* PA Debug */
- {UIC_ARG_MIB(0x9595), 0, 0},
- {UIC_ARG_MIB(0x9597), 0, 0},
- /* DL Debug */
- {UIC_ARG_MIB(0xA000), 0, 0},
- {UIC_ARG_MIB(0xA005), 0, 0},
- {UIC_ARG_MIB(0xA010), 0, 0},
- {UIC_ARG_MIB(0xA114), 0, 0},
- {UIC_ARG_MIB(0xA116), 0, 0},
- /* MPHY PCS Lane 0*/
- {UIC_ARG_MIB_SEL(0x0021, TX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x0022, TX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x0023, TX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x0024, TX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x0028, TX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x0029, TX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x002A, TX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x002B, TX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x002C, TX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x002D, TX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x0033, TX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x0035, TX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x0036, TX_LANE_0+0), 0, 0},
- {UIC_ARG_MIB_SEL(0x0041, TX_LANE_0+0), 0, 0},
{UIC_ARG_MIB_SEL(0x00A1, RX_LANE_0+0), 0, 0},
{UIC_ARG_MIB_SEL(0x00A2, RX_LANE_0+0), 0, 0},
{UIC_ARG_MIB_SEL(0x00A3, RX_LANE_0+0), 0, 0},
{UIC_ARG_MIB_SEL(0x00A4, RX_LANE_0+0), 0, 0},
{UIC_ARG_MIB_SEL(0x00A7, RX_LANE_0+0), 0, 0},
{UIC_ARG_MIB_SEL(0x00C1, RX_LANE_0+0), 0, 0},
- /* MPHY PCS Lane 1*/
- {UIC_ARG_MIB_SEL(0x0021, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0022, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0023, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0024, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0028, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0029, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x002A, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x002B, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x002C, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x002D, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0033, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0035, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0036, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x0041, TX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A1, RX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A2, RX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A3, RX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A4, RX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x00A7, RX_LANE_0+1), 0, 0},
- {UIC_ARG_MIB_SEL(0x00C1, RX_LANE_0+1), 0, 0},
{},
};
-#else
-static struct exynos_ufs_sfr_log ufs_log_sfr[] = {
- {"STD HCI SFR" , LOG_STD_HCI_SFR, 0},
- {"CAPABILITIES" , REG_CONTROLLER_CAPABILITIES, 0},
- {"UFS VERSION" , REG_UFS_VERSION, 0},
- {"PRODUCT ID" , REG_CONTROLLER_DEV_ID, 0},
- {"MANUFACTURE ID" , REG_CONTROLLER_PROD_ID, 0},
- {"INTERRUPT STATUS" , REG_INTERRUPT_STATUS, 0},
- {"INTERRUPT ENABLE" , REG_INTERRUPT_ENABLE, 0},
- {"CONTROLLER STATUS" , REG_CONTROLLER_STATUS, 0},
- {"CONTROLLER ENABLE" , REG_CONTROLLER_ENABLE, 0},
- {"UTP TRANSF REQ INT AGG CNTRL" , REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL, 0},
- {"UTP TRANSF REQ LIST BASE L" , REG_UTP_TRANSFER_REQ_LIST_BASE_L, 0},
- {"UTP TRANSF REQ LIST BASE H" , REG_UTP_TRANSFER_REQ_LIST_BASE_H, 0},
- {"UTP TRANSF REQ DOOR BELL" , REG_UTP_TRANSFER_REQ_DOOR_BELL, 0},
- {"UTP TRANSF REQ LIST CLEAR" , REG_UTP_TRANSFER_REQ_LIST_CLEAR, 0},
- {"UTP TRANSF REQ LIST RUN STOP" , REG_UTP_TRANSFER_REQ_LIST_RUN_STOP, 0},
- {"UTP TASK REQ LIST BASE L" , REG_UTP_TASK_REQ_LIST_BASE_L, 0},
- {"UTP TASK REQ LIST BASE H" , REG_UTP_TASK_REQ_LIST_BASE_H, 0},
- {"UTP TASK REQ DOOR BELL" , REG_UTP_TASK_REQ_DOOR_BELL, 0},
- {"UTP TASK REQ LIST CLEAR" , REG_UTP_TASK_REQ_LIST_CLEAR, 0},
- {"UTP TASK REQ LIST RUN STOP" , REG_UTP_TASK_REQ_LIST_RUN_STOP, 0},
- {"UIC COMMAND" , REG_UIC_COMMAND, 0},
- {"UIC COMMAND ARG1" , REG_UIC_COMMAND_ARG_1, 0},
- {"UIC COMMAND ARG2" , REG_UIC_COMMAND_ARG_2, 0},
- {"UIC COMMAND ARG3" , REG_UIC_COMMAND_ARG_3, 0},
-
- {"VS HCI SFR" , LOG_VS_HCI_SFR, 0},
-
- {"TXPRDT ENTRY SIZE" , HCI_TXPRDT_ENTRY_SIZE, 0},
- {"RXPRDT ENTRY SIZE" , HCI_RXPRDT_ENTRY_SIZE, 0},
- {"TO CNT DIV VAL" , HCI_TO_CNT_DIV_VAL, 0},
- {"1US TO CNT VAL" , HCI_1US_TO_CNT_VAL, 0},
- {"INVALID UPIU CTRL" , HCI_INVALID_UPIU_CTRL, 0},
- {"INVALID UPIU BADDR" , HCI_INVALID_UPIU_BADDR, 0},
- {"INVALID UPIU UBADDR" , HCI_INVALID_UPIU_UBADDR, 0},
- {"INVALID UTMR OFFSET ADDR" , HCI_INVALID_UTMR_OFFSET_ADDR, 0},
- {"INVALID UTR OFFSET ADDR" , HCI_INVALID_UTR_OFFSET_ADDR, 0},
- {"INVALID DIN OFFSET ADDR" , HCI_INVALID_DIN_OFFSET_ADDR, 0},
- {"DBR TIMER CONFIG" , HCI_DBR_TIMER_CONFIG, 0},
- {"DBR TIMER STATUS" , HCI_DBR_TIMER_STATUS, 0},
- {"VENDOR SPECIFIC IS" , HCI_VENDOR_SPECIFIC_IS, 0},
- {"VENDOR SPECIFIC IE" , HCI_VENDOR_SPECIFIC_IE, 0},
- {"UTRL NEXUS TYPE" , HCI_UTRL_NEXUS_TYPE, 0},
- {"UTMRL NEXUS TYPE" , HCI_UTMRL_NEXUS_TYPE, 0},
- {"E2EFC CTRL" , HCI_E2EFC_CTRL, 0},
- {"SW RST" , HCI_SW_RST, 0},
- {"LINK VERSION" , HCI_LINK_VERSION, 0},
- {"IDLE TIMER CONFIG" , HCI_IDLE_TIMER_CONFIG, 0},
- {"RX UPIU MATCH ERROR CODE" , HCI_RX_UPIU_MATCH_ERROR_CODE, 0},
- {"DATA REORDER" , HCI_DATA_REORDER, 0},
- {"MAX DOUT DATA SIZE" , HCI_MAX_DOUT_DATA_SIZE, 0},
- {"UNIPRO APB CLK CTRL" , HCI_UNIPRO_APB_CLK_CTRL, 0},
- {"AXIDMA RWDATA BURST LEN" , HCI_AXIDMA_RWDATA_BURST_LEN, 0},
- {"GPIO OUT" , HCI_GPIO_OUT, 0},
- {"WRITE DMA CTRL" , HCI_WRITE_DMA_CTRL, 0},
- {"ERROR EN PA LAYER" , HCI_ERROR_EN_PA_LAYER, 0},
- {"ERROR EN DL LAYER" , HCI_ERROR_EN_DL_LAYER, 0},
- {"ERROR EN N LAYER" , HCI_ERROR_EN_N_LAYER, 0},
- {"ERROR EN T LAYER" , HCI_ERROR_EN_T_LAYER, 0},
- {"ERROR EN DME LAYER" , HCI_ERROR_EN_DME_LAYER, 0},
- {"REQ HOLD EN" , HCI_REQ_HOLD_EN, 0},
- {"CLKSTOP CTRL" , HCI_CLKSTOP_CTRL, 0},
- {"FORCE HCS" , HCI_FORCE_HCS, 0},
- {"FSM MONITOR" , HCI_FSM_MONITOR, 0},
- {"PRDT HIT RATIO" , HCI_PRDT_HIT_RATIO, 0},
- {"DMA0 MONITOR STATE" , HCI_DMA0_MONITOR_STATE, 0},
- {"DMA0 MONITOR CNT" , HCI_DMA0_MONITOR_CNT, 0},
- {"DMA1 MONITOR STATE" , HCI_DMA1_MONITOR_STATE, 0},
- {"DMA1 MONITOR CNT" , HCI_DMA1_MONITOR_CNT, 0},
-
- {"FMP SFR" , LOG_FMP_SFR, 0},
-
- {"UFSPRCTRL" , UFSPRCTRL, 0},
- {"UFSPRSTAT" , UFSPRSTAT, 0},
- {"UFSPRSECURITY" , UFSPRSECURITY, 0},
- {"UFSPVERSION" , UFSPVERSION, 0},
- {"UFSPWCTRL" , UFSPWCTRL, 0},
- {"UFSPWSTAT" , UFSPWSTAT, 0},
- {"UFSPSBEGIN0" , UFSPSBEGIN0, 0},
- {"UFSPSEND0" , UFSPSEND0, 0},
- {"UFSPSLUN0" , UFSPSLUN0, 0},
- {"UFSPSCTRL0" , UFSPSCTRL0, 0},
- {"UFSPSBEGIN1" , UFSPSBEGIN1, 0},
- {"UFSPSEND1" , UFSPSEND1, 0},
- {"UFSPSLUN1" , UFSPSLUN1, 0},
- {"UFSPSCTRL1" , UFSPSCTRL1, 0},
- {"UFSPSBEGIN2" , UFSPSBEGIN2, 0},
- {"UFSPSEND2" , UFSPSEND2, 0},
- {"UFSPSLUN2" , UFSPSLUN2, 0},
- {"UFSPSCTRL2" , UFSPSCTRL2, 0},
- {"UFSPSBEGIN3" , UFSPSBEGIN3, 0},
- {"UFSPSEND3" , UFSPSEND3, 0},
- {"UFSPSLUN3" , UFSPSLUN3, 0},
- {"UFSPSCTRL3" , UFSPSCTRL3, 0},
- {"UFSPSBEGIN4" , UFSPSBEGIN4, 0},
- {"UFSPSLUN4" , UFSPSLUN4, 0},
- {"UFSPSCTRL4" , UFSPSCTRL4, 0},
- {"UFSPSBEGIN5" , UFSPSBEGIN5, 0},
- {"UFSPSEND5" , UFSPSEND5, 0},
- {"UFSPSLUN5" , UFSPSLUN5, 0},
- {"UFSPSCTRL5" , UFSPSCTRL5, 0},
- {"UFSPSBEGIN6" , UFSPSBEGIN6, 0},
- {"UFSPSEND6" , UFSPSEND6, 0},
- {"UFSPSLUN6" , UFSPSLUN6, 0},
- {"UFSPSCTRL6" , UFSPSCTRL6, 0},
- {"UFSPSBEGIN7" , UFSPSBEGIN7, 0},
- {"UFSPSEND7" , UFSPSEND7, 0},
- {"UFSPSLUN7" , UFSPSLUN7, 0},
- {"UFSPSCTRL7" , UFSPSCTRL7, 0},
-
- {"UNIPRO SFR" , LOG_UNIPRO_SFR, 0},
-
- {"COMP_VERSION" , UNIP_COMP_VERSION , 0},
- {"COMP_INFO" , UNIP_COMP_INFO , 0},
- {"COMP_RESET" , UNIP_COMP_RESET , 0},
- {"DME_POWERON_REQ" , UNIP_DME_POWERON_REQ , 0},
- {"DME_POWERON_CNF_RESULT" , UNIP_DME_POWERON_CNF_RESULT , 0},
- {"DME_POWEROFF_REQ" , UNIP_DME_POWEROFF_REQ , 0},
- {"DME_POWEROFF_CNF_RESULT" , UNIP_DME_POWEROFF_CNF_RESULT , 0},
- {"DME_RESET_REQ" , UNIP_DME_RESET_REQ , 0},
- {"DME_RESET_REQ_LEVEL" , UNIP_DME_RESET_REQ_LEVEL , 0},
- {"DME_ENABLE_REQ" , UNIP_DME_ENABLE_REQ , 0},
- {"DME_ENABLE_CNF_RESULT" , UNIP_DME_ENABLE_CNF_RESULT , 0},
- {"DME_ENDPOINTRESET_REQ" , UNIP_DME_ENDPOINTRESET_REQ , 0},
- {"DME_ENDPOINTRESET_CNF_RESULT" , UNIP_DME_ENDPOINTRESET_CNF_RESULT , 0},
- {"DME_LINKSTARTUP_REQ" , UNIP_DME_LINKSTARTUP_REQ , 0},
- {"DME_LINKSTARTUP_CNF_RESULT" , UNIP_DME_LINKSTARTUP_CNF_RESULT , 0},
- {"DME_HIBERN8_ENTER_REQ" , UNIP_DME_HIBERN8_ENTER_REQ , 0},
- {"DME_HIBERN8_ENTER_CNF_RESULT" , UNIP_DME_HIBERN8_ENTER_CNF_RESULT , 0},
- {"DME_HIBERN8_ENTER_IND_RESULT" , UNIP_DME_HIBERN8_ENTER_IND_RESULT , 0},
- {"DME_HIBERN8_EXIT_REQ" , UNIP_DME_HIBERN8_EXIT_REQ , 0},
- {"DME_HIBERN8_EXIT_CNF_RESULT" , UNIP_DME_HIBERN8_EXIT_CNF_RESULT , 0},
- {"DME_HIBERN8_EXIT_IND_RESULT" , UNIP_DME_HIBERN8_EXIT_IND_RESULT , 0},
- {"DME_PWR_REQ" , UNIP_DME_PWR_REQ , 0},
- {"DME_PWR_REQ_POWERMODE " , UNIP_DME_PWR_REQ_POWERMODE , 0},
- {"DME_PWR_REQ_LOCALL2TIMER0" , UNIP_DME_PWR_REQ_LOCALL2TIMER0 , 0},
- {"DME_PWR_REQ_LOCALL2TIMER1" , UNIP_DME_PWR_REQ_LOCALL2TIMER1 , 0},
- {"DME_PWR_REQ_LOCALL2TIMER2" , UNIP_DME_PWR_REQ_LOCALL2TIMER2 , 0},
- {"DME_PWR_REQ_REMOTEL2TIMER0" , UNIP_DME_PWR_REQ_REMOTEL2TIMER0 , 0},
- {"DME_PWR_REQ_REMOTEL2TIMER1" , UNIP_DME_PWR_REQ_REMOTEL2TIMER1 , 0},
- {"DME_PWR_REQ_REMOTEL2TIMER2" , UNIP_DME_PWR_REQ_REMOTEL2TIMER2 , 0},
- {"DME_PWR_CNF_RESULT" , UNIP_DME_PWR_CNF_RESULT , 0},
- {"DME_PWR_IND_RESULT" , UNIP_DME_PWR_IND_RESULT , 0},
- {"DME_TEST_MODE_REQ" , UNIP_DME_TEST_MODE_REQ , 0},
- {"DME_TEST_MODE_CNF_RESULT" , UNIP_DME_TEST_MODE_CNF_RESULT , 0},
- {"DME_ERROR_IND_LAYER" , UNIP_DME_ERROR_IND_LAYER , 0},
- {"DME_ERROR_IND_ERRCODE" , UNIP_DME_ERROR_IND_ERRCODE , 0},
- {"DME_PACP_CNFBIT" , UNIP_DME_PACP_CNFBIT , 0},
- {"DME_DL_FRAME_IND" , UNIP_DME_DL_FRAME_IND , 0},
- {"DME_INTR_STATUS" , UNIP_DME_INTR_STATUS , 0},
- {"DME_INTR_ENABLE" , UNIP_DME_INTR_ENABLE , 0},
- {"DME_GETSET_ADDR" , UNIP_DME_GETSET_ADDR , 0},
- {"DME_GETSET_WDATA" , UNIP_DME_GETSET_WDATA , 0},
- {"DME_GETSET_RDATA" , UNIP_DME_GETSET_RDATA , 0},
- {"DME_GETSET_CONTROL" , UNIP_DME_GETSET_CONTROL , 0},
- {"DME_GETSET_RESULT" , UNIP_DME_GETSET_RESULT , 0},
- {"DME_PEER_GETSET_ADDR" , UNIP_DME_PEER_GETSET_ADDR , 0},
- {"DME_PEER_GETSET_WDATA" , UNIP_DME_PEER_GETSET_WDATA , 0},
- {"DME_PEER_GETSET_RDATA" , UNIP_DME_PEER_GETSET_RDATA , 0},
- {"DME_PEER_GETSET_CONTROL" , UNIP_DME_PEER_GETSET_CONTROL , 0},
- {"DME_PEER_GETSET_RESULT" , UNIP_DME_PEER_GETSET_RESULT , 0},
- {"DME_DIRECT_GETSET_BASE" , UNIP_DME_DIRECT_GETSET_BASE , 0},
- {"DME_DIRECT_GETSET_ERR_ADDR" , UNIP_DME_DIRECT_GETSET_ERR_ADDR , 0},
- {"DME_DIRECT_GETSET_ERR_CODE" , UNIP_DME_DIRECT_GETSET_ERR_CODE , 0},
- {"DME_INTR_ERROR_CODE" , UNIP_DME_INTR_ERROR_CODE , 0},
- {"DME_DEEPSTALL_ENTER_REQ" , UNIP_DME_DEEPSTALL_ENTER_REQ , 0},
- {"DME_DISCARD_CPORT_ID" , UNIP_DME_DISCARD_CPORT_ID , 0},
- {"DBG_DME_CTRL_STATE" , UNIP_DBG_DME_CTRL_STATE , 0},
- {"DBG_FORCE_DME_CTRL_STATE" , UNIP_DBG_FORCE_DME_CTRL_STATE , 0},
- {"DBG_AUTO_DME_LINKSTARTUP" , UNIP_DBG_AUTO_DME_LINKSTARTUP, 0},
- {"DBG_PA_CTRLSTATE" , UNIP_DBG_PA_CTRLSTATE , 0},
- {"DBG_PA_TX_STATE" , UNIP_DBG_PA_TX_STATE , 0},
- {"DBG_BREAK_DME_CTRL_STATE" , UNIP_DBG_BREAK_DME_CTRL_STATE , 0},
- {"DBG_STEP_DME_CTRL_STATE" , UNIP_DBG_STEP_DME_CTRL_STATE , 0},
- {"DBG_NEXT_DME_CTRL_STATE" , UNIP_DBG_NEXT_DME_CTRL_STATE , 0},
-
- {"PMA SFR" , LOG_PMA_SFR, 0},
-
- {"COMN 0x00" , (0x00<<2), 0},
- {"TRSV 0x31" , (0x31<<2), 0},
-
- {},
-};
-
-static struct exynos_ufs_attr_log ufs_log_attr[] = {
- /* PA Standard */
- {UIC_ARG_MIB(0x1520), 0, 0},
- {UIC_ARG_MIB(0x1540), 0, 0},
- {UIC_ARG_MIB(0x1543), 0, 0},
- {UIC_ARG_MIB(0x155C), 0, 0},
- {UIC_ARG_MIB(0x155D), 0, 0},
- {UIC_ARG_MIB(0x155E), 0, 0},
- {UIC_ARG_MIB(0x155F), 0, 0},
- {UIC_ARG_MIB(0x1560), 0, 0},
- {UIC_ARG_MIB(0x1561), 0, 0},
- {UIC_ARG_MIB(0x1564), 0, 0},
- {UIC_ARG_MIB(0x1567), 0, 0},
- {UIC_ARG_MIB(0x1568), 0, 0},
- {UIC_ARG_MIB(0x1569), 0, 0},
- {UIC_ARG_MIB(0x156A), 0, 0},
- {UIC_ARG_MIB(0x1571), 0, 0},
- {UIC_ARG_MIB(0x1580), 0, 0},
- {UIC_ARG_MIB(0x1581), 0, 0},
- {UIC_ARG_MIB(0x1582), 0, 0},
- {UIC_ARG_MIB(0x1583), 0, 0},
- {UIC_ARG_MIB(0x1584), 0, 0},
- {UIC_ARG_MIB(0x1585), 0, 0},
- {UIC_ARG_MIB(0x1590), 0, 0},
- {UIC_ARG_MIB(0x1591), 0, 0},
- {UIC_ARG_MIB(0x15A1), 0, 0},
- {UIC_ARG_MIB(0x15A2), 0, 0},
- {UIC_ARG_MIB(0x15A3), 0, 0},
- {UIC_ARG_MIB(0x15A4), 0, 0},
- {UIC_ARG_MIB(0x15A7), 0, 0},
- {UIC_ARG_MIB(0x15A8), 0, 0},
- {UIC_ARG_MIB(0x15C0), 0, 0},
- {UIC_ARG_MIB(0x15C1), 0, 0},
- /* PA Debug */
-
- /* DL Standard */
- {UIC_ARG_MIB(0x2002), 0, 0},
- {UIC_ARG_MIB(0x2003), 0, 0},
- {UIC_ARG_MIB(0x2004), 0, 0},
- {UIC_ARG_MIB(0x2005), 0, 0},
- {UIC_ARG_MIB(0x2006), 0, 0},
- {UIC_ARG_MIB(0x2040), 0, 0},
- {UIC_ARG_MIB(0x2041), 0, 0},
- {UIC_ARG_MIB(0x2042), 0, 0},
- {UIC_ARG_MIB(0x2043), 0, 0},
- {UIC_ARG_MIB(0x2044), 0, 0},
- {UIC_ARG_MIB(0x2045), 0, 0},
- {UIC_ARG_MIB(0x2046), 0, 0},
- {UIC_ARG_MIB(0x2047), 0, 0},
- {UIC_ARG_MIB(0x2060), 0, 0},
- {UIC_ARG_MIB(0x2061), 0, 0},
- {UIC_ARG_MIB(0x2062), 0, 0},
- {UIC_ARG_MIB(0x2063), 0, 0},
- {UIC_ARG_MIB(0x2064), 0, 0},
- {UIC_ARG_MIB(0x2065), 0, 0},
- {UIC_ARG_MIB(0x2066), 0, 0},
- {UIC_ARG_MIB(0x2067), 0, 0},
-
- /* DL Debug */
-
- /* NL Standard */
- {UIC_ARG_MIB(0x3000), 0, 0},
- {UIC_ARG_MIB(0x3001), 0, 0},
- {UIC_ARG_MIB(0x4020), 0, 0},
- {UIC_ARG_MIB(0x4021), 0, 0},
- {UIC_ARG_MIB(0x4022), 0, 0},
- {UIC_ARG_MIB(0x4023), 0, 0},
- {UIC_ARG_MIB(0x4025), 0, 0},
- {UIC_ARG_MIB(0x402B), 0, 0},
-
- /* MPHY PCS Lane 0 Standard*/
- {UIC_ARG_MIB(0x0021), 0, 0},
- {UIC_ARG_MIB(0x0022), 0, 0},
- {UIC_ARG_MIB(0x0023), 0, 0},
- {UIC_ARG_MIB(0x0024), 0, 0},
- {UIC_ARG_MIB(0x0028), 0, 0},
- {UIC_ARG_MIB(0x0029), 0, 0},
- {UIC_ARG_MIB(0x002A), 0, 0},
- {UIC_ARG_MIB(0x002B), 0, 0},
- {UIC_ARG_MIB(0x002C), 0, 0},
- {UIC_ARG_MIB(0x002D), 0, 0},
- {UIC_ARG_MIB(0x0033), 0, 0},
- {UIC_ARG_MIB(0x0035), 0, 0},
- {UIC_ARG_MIB(0x0036), 0, 0},
- {UIC_ARG_MIB(0x0041), 0, 0},
-
- {UIC_ARG_MIB(0x00A1), 0, 0},
- {UIC_ARG_MIB(0x00A2), 0, 0},
- {UIC_ARG_MIB(0x00A3), 0, 0},
- {UIC_ARG_MIB(0x00A4), 0, 0},
- {UIC_ARG_MIB(0x00A7), 0, 0},
- {UIC_ARG_MIB(0x00C1), 0, 0},
-
- {},
-};
-
-static struct exynos_ufs_sfr_log ufs_show_sfr[] = {
- {},
-};
-
-static struct exynos_ufs_attr_log ufs_show_attr[] = {
- {},
-};
-
-#endif
static void exynos_ufs_get_misc(struct ufs_hba *hba)
{
struct exynos_ufs *ufs = to_exynos_ufs(hba);
projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / commitdiff