ARM: tegra: add clk_prepare/clk_unprepare
authorPrashant Gaikwad <pgaikwad@nvidia.com>
Tue, 5 Jun 2012 04:29:35 +0000 (09:59 +0530)
committerStephen Warren <swarren@nvidia.com>
Mon, 11 Jun 2012 17:53:29 +0000 (11:53 -0600)
Use clk_prepare/clk_unprepare as required by the generic clk framework.

Tested on Ventana and Cardhu.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
arch/arm/mach-tegra/cpu-tegra.c
arch/arm/mach-tegra/dma.c
arch/arm/mach-tegra/pcie.c
arch/arm/mach-tegra/powergate.c
arch/arm/mach-tegra/timer.c
arch/arm/mach-tegra/usb_phy.c

index 7a065f0cf6338dfa6566b23d7a48e318c843a1f9..ceb52db1e2f16409729c2ef0205b854163a3fae7 100644 (file)
@@ -189,8 +189,8 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
                return PTR_ERR(emc_clk);
        }
 
-       clk_enable(emc_clk);
-       clk_enable(cpu_clk);
+       clk_prepare_enable(emc_clk);
+       clk_prepare_enable(cpu_clk);
 
        cpufreq_frequency_table_cpuinfo(policy, freq_table);
        cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
@@ -212,7 +212,7 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
 static int tegra_cpu_exit(struct cpufreq_policy *policy)
 {
        cpufreq_frequency_table_cpuinfo(policy, freq_table);
-       clk_disable(emc_clk);
+       clk_disable_unprepare(emc_clk);
        clk_put(emc_clk);
        clk_put(cpu_clk);
        return 0;
index abea4f6e2dd5cbc47aeb3a516fea05d27afe08d4..2698d7d5c9cab17235bc9aba0149503e1799ffda 100644 (file)
@@ -720,7 +720,7 @@ int __init tegra_dma_init(void)
                ret = PTR_ERR(c);
                goto fail;
        }
-       ret = clk_enable(c);
+       ret = clk_prepare_enable(c);
        if (ret != 0) {
                pr_err("Unable to enable clock for APB DMA\n");
                goto fail;
index 0e09137506ec79890b56f76c47ac9e0bc8b225d9..d3ad5150d6609e135a063421d2c9acad62e204df 100644 (file)
@@ -723,9 +723,9 @@ static int tegra_pcie_power_regate(void)
 
        tegra_pcie_xclk_clamp(false);
 
-       clk_enable(tegra_pcie.afi_clk);
-       clk_enable(tegra_pcie.pex_clk);
-       return clk_enable(tegra_pcie.pll_e);
+       clk_prepare_enable(tegra_pcie.afi_clk);
+       clk_prepare_enable(tegra_pcie.pex_clk);
+       return clk_prepare_enable(tegra_pcie.pll_e);
 }
 
 static int tegra_pcie_clocks_get(void)
index f5b12fb4ff12306563fd5da0152230424118a843..15d506501cccbb64dc25e5a1178bd91d40e94901 100644 (file)
@@ -146,7 +146,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
        if (ret)
                goto err_power;
 
-       ret = clk_enable(clk);
+       ret = clk_prepare_enable(clk);
        if (ret)
                goto err_clk;
 
@@ -162,7 +162,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
        return 0;
 
 err_clamp:
-       clk_disable(clk);
+       clk_disable_unprepare(clk);
 err_clk:
        tegra_powergate_power_off(id);
 err_power:
index 315672c7bd48f09e4c684fdb048cafde0857ab2c..57b5bdc13b9b9525b227e05e85907d508e2617c5 100644 (file)
@@ -189,7 +189,7 @@ static void __init tegra_init_timer(void)
                        " Assuming 12Mhz input clock.\n");
                rate = 12000000;
        } else {
-               clk_enable(clk);
+               clk_prepare_enable(clk);
                rate = clk_get_rate(clk);
        }
 
@@ -201,7 +201,7 @@ static void __init tegra_init_timer(void)
        if (IS_ERR(clk))
                pr_warn("Unable to get rtc-tegra clock\n");
        else
-               clk_enable(clk);
+               clk_prepare_enable(clk);
 
        switch (rate) {
        case 12000000:
index 54e353c8e3042f61e7c487c16f1cd29d22758fb6..022b33a05c3a22f8586d835271d26508abbdbab4 100644 (file)
@@ -247,7 +247,7 @@ static void utmip_pad_power_on(struct tegra_usb_phy *phy)
        unsigned long val, flags;
        void __iomem *base = phy->pad_regs;
 
-       clk_enable(phy->pad_clk);
+       clk_prepare_enable(phy->pad_clk);
 
        spin_lock_irqsave(&utmip_pad_lock, flags);
 
@@ -259,7 +259,7 @@ static void utmip_pad_power_on(struct tegra_usb_phy *phy)
 
        spin_unlock_irqrestore(&utmip_pad_lock, flags);
 
-       clk_disable(phy->pad_clk);
+       clk_disable_unprepare(phy->pad_clk);
 }
 
 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
@@ -272,7 +272,7 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
                return -EINVAL;
        }
 
-       clk_enable(phy->pad_clk);
+       clk_prepare_enable(phy->pad_clk);
 
        spin_lock_irqsave(&utmip_pad_lock, flags);
 
@@ -284,7 +284,7 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
 
        spin_unlock_irqrestore(&utmip_pad_lock, flags);
 
-       clk_disable(phy->pad_clk);
+       clk_disable_unprepare(phy->pad_clk);
 
        return 0;
 }
@@ -580,7 +580,7 @@ static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
        msleep(5);
        gpio_direction_output(config->reset_gpio, 1);
 
-       clk_enable(phy->clk);
+       clk_prepare_enable(phy->clk);
        msleep(1);
 
        val = readl(base + USB_SUSP_CTRL);
@@ -689,7 +689,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
                err = PTR_ERR(phy->pll_u);
                goto err0;
        }
-       clk_enable(phy->pll_u);
+       clk_prepare_enable(phy->pll_u);
 
        parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
        for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
@@ -735,7 +735,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
        return phy;
 
 err1:
-       clk_disable(phy->pll_u);
+       clk_disable_unprepare(phy->pll_u);
        clk_put(phy->pll_u);
 err0:
        kfree(phy);
@@ -810,7 +810,7 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy)
                clk_put(phy->clk);
        else
                utmip_pad_close(phy);
-       clk_disable(phy->pll_u);
+       clk_disable_unprepare(phy->pll_u);
        clk_put(phy->pll_u);
        kfree(phy);
 }