perf, x86: Add new AMD family 15h msrs to perfctr reservation code
authorRobert Richter <robert.richter@amd.com>
Wed, 2 Feb 2011 16:40:58 +0000 (17:40 +0100)
committerIngo Molnar <mingo@elte.hu>
Wed, 16 Feb 2011 12:30:50 +0000 (13:30 +0100)
This patch allows the reservation of perfctrs with new msr addresses
introduced for AMD cpu family 15h (0xc0010200/0xc0010201, etc).

Signed-off-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <1296664860-10886-4-git-send-email-robert.richter@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/perfctr-watchdog.c

index d5a236615501fd6a41fb6f6bc76bfd2369a47bc5..966512b2cacf37824bc2b2bccda04e6f26f12ddf 100644 (file)
@@ -46,6 +46,8 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
        /* returns the bit offset of the performance counter register */
        switch (boot_cpu_data.x86_vendor) {
        case X86_VENDOR_AMD:
+               if (msr >= MSR_F15H_PERF_CTR)
+                       return (msr - MSR_F15H_PERF_CTR) >> 1;
                return msr - MSR_K7_PERFCTR0;
        case X86_VENDOR_INTEL:
                if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
@@ -70,6 +72,8 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
        /* returns the bit offset of the event selection register */
        switch (boot_cpu_data.x86_vendor) {
        case X86_VENDOR_AMD:
+               if (msr >= MSR_F15H_PERF_CTL)
+                       return (msr - MSR_F15H_PERF_CTL) >> 1;
                return msr - MSR_K7_EVNTSEL0;
        case X86_VENDOR_INTEL:
                if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))