hdmirx: optimize esm clock init sequence [1/1]
authoryicheng shen <yicheng.shen@amlogic.com>
Thu, 5 Sep 2019 10:24:31 +0000 (06:24 -0400)
committerTao Zeng <tao.zeng@amlogic.com>
Fri, 6 Sep 2019 06:23:11 +0000 (23:23 -0700)
PD#SWPL-13779

Problem:
esm can not work after burning a new key and regenerating new
fw.le as the esm clock was not configured when probe.

Solution:
so we need to configure ESM clock no matter hdcp2.2
is burned or not.

Verify:
None

Change-Id: I793b63ad2f20434b9f8f27ccca7c80dee2990718
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h

index 0800224efb7421422aa1c7f0960936675306c24a..060a998a159b7fde096b6949c9bc08b987c5a0d1 100644 (file)
@@ -2309,25 +2309,24 @@ static int hdmirx_probe(struct platform_device *pdev)
        }
 
        hdcp22_on = rx_is_hdcp22_support();
-       if (hdcp22_on) {
-               hdevp->esm_clk = clk_get(&pdev->dev, "hdcp_rx22_esm");
-               if (IS_ERR(hdevp->esm_clk)) {
-                       rx_pr("get esm_clk err\n");
-               } else {
-                       clk_set_parent(hdevp->esm_clk, fclk_div7_clk);
-                       clk_set_rate(hdevp->esm_clk, 285714285);
-                       clk_prepare_enable(hdevp->esm_clk);
-                       clk_rate = clk_get_rate(hdevp->esm_clk);
-               }
-               hdevp->skp_clk = clk_get(&pdev->dev, "hdcp_rx22_skp");
-               if (IS_ERR(hdevp->skp_clk)) {
-                       rx_pr("get skp_clk err\n");
-               } else {
-                       clk_set_parent(hdevp->skp_clk, xtal_clk);
-                       clk_set_rate(hdevp->skp_clk, 24000000);
-                       clk_prepare_enable(hdevp->skp_clk);
-                       clk_rate = clk_get_rate(hdevp->skp_clk);
-               }
+
+       hdevp->esm_clk = clk_get(&pdev->dev, "hdcp_rx22_esm");
+       if (IS_ERR(hdevp->esm_clk)) {
+               rx_pr("get esm_clk err\n");
+       } else {
+               clk_set_parent(hdevp->esm_clk, fclk_div7_clk);
+               clk_set_rate(hdevp->esm_clk, 285714285);
+               clk_prepare_enable(hdevp->esm_clk);
+               clk_rate = clk_get_rate(hdevp->esm_clk);
+       }
+       hdevp->skp_clk = clk_get(&pdev->dev, "hdcp_rx22_skp");
+       if (IS_ERR(hdevp->skp_clk)) {
+               rx_pr("get skp_clk err\n");
+       } else {
+               clk_set_parent(hdevp->skp_clk, xtal_clk);
+               clk_set_rate(hdevp->skp_clk, 24000000);
+               clk_prepare_enable(hdevp->skp_clk);
+               clk_rate = clk_get_rate(hdevp->skp_clk);
        }
        if ((rx.chip_id == CHIP_ID_TXLX) ||
                (rx.chip_id == CHIP_ID_TXHD)) {
index 12574bdee8e6862fd1c0e01fcd72050313d143dd..7c137e748ecefe1b42e580a7ed3ca4344e89d46d 100644 (file)
@@ -41,7 +41,7 @@
  *
  *
  */
-#define RX_VER1 "ver.2019/07/19"
+#define RX_VER1 "ver.2019/09/05"
 /*
  *
  *