Watchdog: fix clearing of the watchdog interrupt

The bits in BRIDGE_CAUSE are documented as RW0C - read, write 0 to
clear.  If we read the register, mask off the watchdog bit, and
write it back, we're actually clearing every interrupt which wasn't
pending at the time we read the register - and that is racy.

Fix this to only write ~WATCHDOG_BIT to the register, which means
we write as zero only the watchdog bit.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>

diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c
index 4074244c71834f2b2648395437b95a95a7c9fe9b..4ea5fcccac02d1ee6f933cc1e5b8b8e0260da3a4 100644 (file)
--- a/drivers/watchdog/orion_wdt.c
+++ b/drivers/watchdog/orion_wdt.c
@@ -70,9 +70,7 @@ static int orion_wdt_start(struct watchdog_device *wdt_dev)
        writel(wdt_tclk * wdt_dev->timeout, wdt_reg + WDT_VAL);
 
        /* Clear watchdog timer interrupt */
-       reg = readl(BRIDGE_CAUSE);
-       reg &= ~WDT_INT_REQ;
-       writel(reg, BRIDGE_CAUSE);
+       writel(~WDT_INT_REQ, BRIDGE_CAUSE);
 
        /* Enable watchdog timer */
        reg = readl(wdt_reg + TIMER_CTRL);