#define nvxx_device(a) ({ \
struct nvif_device *_device = (a); \
- nv_device(_device->object.priv); \
+ struct { \
+ struct nvkm_object object; \
+ struct nvkm_device *device; \
+ } *_udevice = _device->object.priv; \
+ _udevice->device; \
})
#define nvxx_bios(a) nvxx_device(a)->bios
#define nvxx_fb(a) nvxx_device(a)->fb
#ifndef __NVKM_DEVICE_H__
#define __NVKM_DEVICE_H__
-#include <core/engine.h>
#include <core/event.h>
+#include <core/object.h>
enum nvkm_devidx {
- NVDEV_SUBDEV_VBIOS,
-
- /* All subdevs from DEVINIT to DEVINIT_LAST will be created before
- * *any* of them are initialised. This subdev category is used
- * for any subdevs that the VBIOS init table parsing may call out
- * to during POST.
- */
- NVDEV_SUBDEV_DEVINIT,
- NVDEV_SUBDEV_IBUS,
- NVDEV_SUBDEV_GPIO,
- NVDEV_SUBDEV_I2C,
- NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C,
-
- /* This grouping of subdevs are initialised right after they've
- * been created, and are allowed to assume any subdevs in the
- * list above them exist and have been initialised.
- */
- NVDEV_SUBDEV_FUSE,
- NVDEV_SUBDEV_MXM,
- NVDEV_SUBDEV_MC,
- NVDEV_SUBDEV_BUS,
- NVDEV_SUBDEV_TIMER,
- NVDEV_SUBDEV_FB,
- NVDEV_SUBDEV_LTC,
- NVDEV_SUBDEV_INSTMEM,
- NVDEV_SUBDEV_MMU,
- NVDEV_SUBDEV_BAR,
- NVDEV_SUBDEV_PMU,
- NVDEV_SUBDEV_VOLT,
- NVDEV_SUBDEV_THERM,
- NVDEV_SUBDEV_CLK,
-
- NVDEV_ENGINE_FIRST,
- NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
- NVDEV_ENGINE_IFB,
- NVDEV_ENGINE_FIFO,
- NVDEV_ENGINE_SW,
- NVDEV_ENGINE_GR,
- NVDEV_ENGINE_MPEG,
- NVDEV_ENGINE_ME,
- NVDEV_ENGINE_VP,
- NVDEV_ENGINE_CIPHER,
- NVDEV_ENGINE_BSP,
- NVDEV_ENGINE_MSPPP,
- NVDEV_ENGINE_CE0,
- NVDEV_ENGINE_CE1,
- NVDEV_ENGINE_CE2,
- NVDEV_ENGINE_VIC,
- NVDEV_ENGINE_MSENC,
- NVDEV_ENGINE_DISP,
- NVDEV_ENGINE_PM,
- NVDEV_ENGINE_MSVLD,
- NVDEV_ENGINE_SEC,
- NVDEV_ENGINE_MSPDEC,
-
- NVDEV_SUBDEV_NR,
+ NVKM_SUBDEV_VBIOS,
+ NVKM_SUBDEV_DEVINIT,
+ NVKM_SUBDEV_IBUS,
+ NVKM_SUBDEV_GPIO,
+ NVKM_SUBDEV_I2C,
+ NVKM_SUBDEV_FUSE,
+ NVKM_SUBDEV_MXM,
+ NVKM_SUBDEV_MC,
+ NVKM_SUBDEV_BUS,
+ NVKM_SUBDEV_TIMER,
+ NVKM_SUBDEV_FB,
+ NVKM_SUBDEV_LTC,
+ NVKM_SUBDEV_INSTMEM,
+ NVKM_SUBDEV_MMU,
+ NVKM_SUBDEV_BAR,
+ NVKM_SUBDEV_PMU,
+ NVKM_SUBDEV_VOLT,
+ NVKM_SUBDEV_THERM,
+ NVKM_SUBDEV_CLK,
+
+ NVKM_ENGINE_DMAOBJ,
+ NVKM_ENGINE_IFB,
+ NVKM_ENGINE_FIFO,
+ NVKM_ENGINE_SW,
+ NVKM_ENGINE_GR,
+ NVKM_ENGINE_MPEG,
+ NVKM_ENGINE_ME,
+ NVKM_ENGINE_VP,
+ NVKM_ENGINE_CIPHER,
+ NVKM_ENGINE_BSP,
+ NVKM_ENGINE_MSPPP,
+ NVKM_ENGINE_CE0,
+ NVKM_ENGINE_CE1,
+ NVKM_ENGINE_CE2,
+ NVKM_ENGINE_VIC,
+ NVKM_ENGINE_MSENC,
+ NVKM_ENGINE_DISP,
+ NVKM_ENGINE_PM,
+ NVKM_ENGINE_MSVLD,
+ NVKM_ENGINE_SEC,
+ NVKM_ENGINE_MSPDEC,
+
+ NVKM_SUBDEV_NR,
};
struct nvkm_device {
- struct nvkm_engine engine;
-
const struct nvkm_device_func *func;
const struct nvkm_device_quirk *quirk;
struct device *dev;
struct nvkm_event event;
u64 disable_mask;
+ u32 debug;
const struct nvkm_device_chip *chip;
enum {
u8 chiprev;
u32 crystal;
- struct nvkm_oclass *oclass[NVDEV_SUBDEV_NR];
-
struct {
struct notifier_block nb;
} acpi;
_temp; \
})
-struct nvkm_device *nv_device(void *obj);
-
static inline bool
nv_device_match(struct nvkm_device *device, u16 dev, u16 ven, u16 sub)
{
/* device logging */
#define nvdev_printk_(d,l,p,f,a...) do { \
struct nvkm_device *_device = (d); \
- if (_device->engine.subdev.debug >= (l)) \
+ if (_device->debug >= (l)) \
dev_##p(_device->dev, f, ##a); \
} while(0)
#define nvdev_printk(d,l,p,f,a...) nvdev_printk_((d), NV_DBG_##l, p, f, ##a)
#ifndef __NVKM_ENGINE_H__
#define __NVKM_ENGINE_H__
+#define nvkm_engine(p) container_of((p), struct nvkm_engine, subdev)
#include <core/subdev.h>
-struct nvkm_device_oclass; /*XXX: DEV!ENG */
struct nvkm_fifo_chan;
struct nvkm_fb_tile;
-#define NV_ENGINE_(eng,var) (((var) << 8) | (eng))
-#define NV_ENGINE(name,var) NV_ENGINE_(NVDEV_ENGINE_##name, (var))
-
struct nvkm_engine {
- struct nvkm_subdev subdev;
const struct nvkm_engine_func *func;
+ struct nvkm_subdev subdev;
+ spinlock_t lock;
int usecount;
-
- struct nvkm_oclass *cclass;
- struct nvkm_oclass *sclass;
-
- struct list_head contexts;
- spinlock_t lock;
};
struct nvkm_engine_func {
struct nvkm_engine *nvkm_engine_ref(struct nvkm_engine *);
void nvkm_engine_unref(struct nvkm_engine **);
void nvkm_engine_tile(struct nvkm_engine *, int region);
-
-static inline struct nvkm_engine *
-nv_engine(void *obj)
-{
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
- BUG_ON(!nv_iclass(obj, NV_ENGINE_CLASS));
-#endif
- return obj;
-}
-
-static inline int
-nv_engidx(struct nvkm_engine *engine)
-{
- return nv_subidx(&engine->subdev);
-}
-
-struct nvkm_engine *nvkm_engine(void *obj, int idx);
-
-#define nvkm_engine_create(p,e,c,d,i,f,r) \
- nvkm_engine_create_((p), (e), (c), (d), (i), (f), \
- sizeof(**r),(void **)r)
-
-#define nvkm_engine_destroy(p) \
- nvkm_subdev_destroy(&(p)->subdev)
-#define nvkm_engine_init_old(p) \
- nvkm_subdev_init_old(&(p)->subdev)
-#define nvkm_engine_fini_old(p,s) \
- nvkm_subdev_fini_old(&(p)->subdev, (s))
-
-int nvkm_engine_create_(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, bool, const char *,
- const char *, int, void **);
-
-#define _nvkm_engine_dtor _nvkm_subdev_dtor
-#define _nvkm_engine_init _nvkm_subdev_init
-#define _nvkm_engine_fini _nvkm_subdev_fini
-
-#include <core/device.h>
#endif
void (*wr32)(struct nvkm_gpuobj *, u32 offset, u32 data);
};
-int nvkm_gpuobj_new(struct nvkm_device *, u32 size, int align, bool zero,
- struct nvkm_gpuobj *parent, struct nvkm_gpuobj **);
+int nvkm_gpuobj_new(struct nvkm_device *, u32 size, int align, bool zero,
+ struct nvkm_gpuobj *parent, struct nvkm_gpuobj **);
void nvkm_gpuobj_del(struct nvkm_gpuobj **);
-
-static inline struct nvkm_gpuobj *
-nv_gpuobj(void *obj)
-{
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
- BUG_ON(!nv_iclass(obj, NV_GPUOBJ_CLASS));
-#endif
- return obj;
-}
-
-#define nvkm_gpuobj_create(p,e,c,v,g,s,a,f,d) \
- nvkm_gpuobj_create_((p), (e), (c), (v), (g), (s), (a), (f), \
- sizeof(**d), (void **)d)
-#define nvkm_gpuobj_init(p) _nvkm_object_init(&(p)->object)
-#define nvkm_gpuobj_fini(p,s) _nvkm_object_fini(&(p)->object, (s))
-int nvkm_gpuobj_create_(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, u32 pclass,
- struct nvkm_object *, u32 size, u32 align,
- u32 flags, int length, void **);
-void nvkm_gpuobj_destroy(struct nvkm_gpuobj *);
-
int nvkm_gpuobj_wrap(struct nvkm_memory *, struct nvkm_gpuobj **);
int nvkm_gpuobj_map(struct nvkm_gpuobj *, struct nvkm_vm *, u32 access,
struct nvkm_vma *);
void nvkm_gpuobj_unmap(struct nvkm_vma *);
-
-static inline void
-nvkm_gpuobj_ref(struct nvkm_gpuobj *obj, struct nvkm_gpuobj **ref)
-{
- nvkm_object_ref(&obj->object, (struct nvkm_object **)ref);
-}
-
-void _nvkm_gpuobj_dtor(struct nvkm_object *);
-int _nvkm_gpuobj_init(struct nvkm_object *);
-int _nvkm_gpuobj_fini(struct nvkm_object *, bool);
-u32 _nvkm_gpuobj_rd32(struct nvkm_object *, u64);
-void _nvkm_gpuobj_wr32(struct nvkm_object *, u64, u32);
#endif
#include <core/debug.h>
struct nvkm_event;
struct nvkm_gpuobj;
-
-#define NV_PARENT_CLASS 0x80000000
-#define NV_NAMEDB_CLASS 0x40000000
-#define NV_CLIENT_CLASS 0x20000000
-#define NV_SUBDEV_CLASS 0x10000000
-#define NV_ENGINE_CLASS 0x08000000
-#define NV_MEMOBJ_CLASS 0x04000000
-#define NV_GPUOBJ_CLASS 0x02000000
-#define NV_ENGCTX_CLASS 0x01000000
+struct nvkm_oclass;
struct nvkm_object {
const struct nvkm_object_func *func;
struct nvkm_client *client;
struct nvkm_engine *engine;
- u32 oclass_name;
+ u32 oclass;
u32 handle;
struct nvkm_object *parent;
- struct nvkm_oclass *oclass;
u32 pclass;
atomic_t refcount;
atomic_t usecount;
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
-#define NVKM_OBJECT_MAGIC 0x75ef0bad
- struct list_head list;
- u32 _magic;
-#endif
};
struct nvkm_object_func {
int nvkm_object_bind(struct nvkm_object *, struct nvkm_gpuobj *, int align,
struct nvkm_gpuobj **);
-static inline struct nvkm_object *
-nv_object(void *obj)
-{
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
- if (likely(obj)) {
- struct nvkm_object *object = obj;
- BUG_ON(object->_magic != NVKM_OBJECT_MAGIC);
- }
-#endif
- return obj;
-}
-
-#define nvkm_object_create(p,e,c,s,d) \
- nvkm_object_create_((p), (e), (c), (s), sizeof(**d), (void **)d)
-int nvkm_object_create_(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, u32, int size, void **);
-void nvkm_object_destroy(struct nvkm_object *);
-int _nvkm_object_init(struct nvkm_object *);
-int _nvkm_object_fini(struct nvkm_object *, bool suspend);
-
-int _nvkm_object_ctor(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, void *, u32,
- struct nvkm_object **);
-
-extern struct nvkm_ofuncs nvkm_object_ofuncs;
-
struct nvkm_sclass {
int minver;
int maxver;
};
struct nvkm_oclass {
- s32 handle;
- struct nvkm_ofuncs * const ofuncs;
-
int (*ctor)(const struct nvkm_oclass *, void *data, u32 size,
struct nvkm_object **);
struct nvkm_sclass base;
const void *priv;
const void *engn;
+ s32 handle;
u64 object;
struct nvkm_client *client;
struct nvkm_object *parent;
struct nvkm_engine *engine;
};
-#define nv_oclass(o) nv_object(o)->oclass
-#define nv_hclass(o) nv_oclass(o)->handle
-#define nv_iclass(o,i) (nv_object(o)->pclass & (i))
-#define nv_mclass(o) nv_oclass(o)->handle
-
-static inline struct nvkm_object *
-nv_pclass(struct nvkm_object *parent, u32 oclass)
-{
- while (parent && !nv_iclass(parent, oclass))
- parent = parent->parent;
- return parent;
-}
-
-struct nvkm_ofuncs {
- int (*ctor)(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, void *data, u32 size,
- struct nvkm_object **);
- void (*dtor)(struct nvkm_object *);
- int (*init)(struct nvkm_object *);
- int (*fini)(struct nvkm_object *, bool suspend);
- int (*mthd)(struct nvkm_object *, u32, void *, u32);
- int (*ntfy)(struct nvkm_object *, u32, struct nvkm_event **);
- int (* map)(struct nvkm_object *, u64 *, u32 *);
- u8 (*rd08)(struct nvkm_object *, u64 offset);
- u16 (*rd16)(struct nvkm_object *, u64 offset);
- u32 (*rd32)(struct nvkm_object *, u64 offset);
- void (*wr08)(struct nvkm_object *, u64 offset, u8 data);
- void (*wr16)(struct nvkm_object *, u64 offset, u16 data);
- void (*wr32)(struct nvkm_object *, u64 offset, u32 data);
-};
-
-static inline struct nvkm_ofuncs *
-nv_ofuncs(void *obj)
-{
- return nv_oclass(obj)->ofuncs;
-}
-
-int nvkm_object_old(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, void *, u32,
- struct nvkm_object **);
void nvkm_object_ref(struct nvkm_object *, struct nvkm_object **);
int nvkm_object_inc(struct nvkm_object *);
int nvkm_object_dec(struct nvkm_object *, bool suspend);
#ifndef __NVKM_SUBDEV_H__
#define __NVKM_SUBDEV_H__
-#include <core/object.h>
-
-#define NV_SUBDEV_(sub,var) (((var) << 8) | (sub))
-#define NV_SUBDEV(name,var) NV_SUBDEV_(NVDEV_SUBDEV_##name, (var))
+#include <core/device.h>
struct nvkm_subdev {
- struct nvkm_object object;
const struct nvkm_subdev_func *func;
struct nvkm_device *device;
- int index;
+ enum nvkm_devidx index;
u32 pmc_enable;
-
struct mutex mutex;
u32 debug;
- bool oneinit;
- void (*intr)(struct nvkm_subdev *);
- u32 unit;
+ bool oneinit;
};
struct nvkm_subdev_func {
void (*intr)(struct nvkm_subdev *);
};
-extern const char *nvkm_subdev_name[64];
+extern const char *nvkm_subdev_name[NVKM_SUBDEV_NR];
void nvkm_subdev_ctor(const struct nvkm_subdev_func *, struct nvkm_device *,
int index, u32 pmc_enable, struct nvkm_subdev *);
void nvkm_subdev_del(struct nvkm_subdev **);
int nvkm_subdev_fini(struct nvkm_subdev *, bool suspend);
void nvkm_subdev_intr(struct nvkm_subdev *);
-static inline struct nvkm_subdev *
-nv_subdev(void *obj)
-{
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
- BUG_ON(!nv_iclass(obj, NV_SUBDEV_CLASS));
-#endif
- return obj;
-}
-
-static inline int
-nv_subidx(struct nvkm_subdev *subdev)
-{
- return nv_hclass(subdev) & 0xff;
-}
-
-struct nvkm_subdev *nvkm_subdev(void *obj, int idx);
-
-#define nvkm_subdev_create(p,e,o,v,s,f,d) \
- nvkm_subdev_create_((p), (e), (o), (v), (s), (f), \
- sizeof(**d),(void **)d)
-
-int nvkm_subdev_create_(struct nvkm_object *, struct nvkm_object *,
- struct nvkm_oclass *, u32 pclass,
- const char *sname, const char *fname,
- int size, void **);
-void nvkm_subdev_destroy(struct nvkm_subdev *);
-int nvkm_subdev_init_old(struct nvkm_subdev *);
-int nvkm_subdev_fini_old(struct nvkm_subdev *, bool suspend);
-void nvkm_subdev_reset(struct nvkm_object *);
-
-void _nvkm_subdev_dtor(struct nvkm_object *);
-int _nvkm_subdev_init(struct nvkm_object *);
-int _nvkm_subdev_fini(struct nvkm_object *, bool suspend);
-
/* subdev logging */
#define nvkm_printk_(s,l,p,f,a...) do { \
struct nvkm_subdev *_subdev = (s); \
#define nvkm_debug(s,f,a...) nvkm_printk((s), DEBUG, info, f, ##a)
#define nvkm_trace(s,f,a...) nvkm_printk((s), TRACE, info, f, ##a)
#define nvkm_spam(s,f,a...) nvkm_printk((s), SPAM, dbg, f, ##a)
-
-#include <core/engine.h>
#endif
u64 addr;
u32 size;
- struct nvkm_fifo_engn engn[NVDEV_SUBDEV_NR];
+ struct nvkm_fifo_engn engn[NVKM_SUBDEV_NR];
};
-extern const struct nvkm_object_func nvkm_fifo_chan_func;
-
struct nvkm_fifo {
const struct nvkm_fifo_func *func;
struct nvkm_engine engine;
struct kref refcount;
struct list_head pgd_list;
- atomic_t engref[NVDEV_SUBDEV_NR];
+ atomic_t engref[NVKM_SUBDEV_NR];
struct nvkm_vm_pgt *pgt;
u32 fpde;
}
static void
-nvkm_engine_intr(struct nvkm_subdev *obj)
+nvkm_engine_intr(struct nvkm_subdev *subdev)
{
- struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev);
+ struct nvkm_engine *engine = nvkm_engine(subdev);
if (engine->func->intr)
engine->func->intr(engine);
}
static int
-nvkm_engine_fini(struct nvkm_subdev *obj, bool suspend)
+nvkm_engine_fini(struct nvkm_subdev *subdev, bool suspend)
{
- struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev);
- if (engine->subdev.object.oclass)
- return engine->subdev.object.oclass->ofuncs->fini(&engine->subdev.object, suspend);
+ struct nvkm_engine *engine = nvkm_engine(subdev);
if (engine->func->fini)
return engine->func->fini(engine, suspend);
return 0;
}
static int
-nvkm_engine_init(struct nvkm_subdev *obj)
+nvkm_engine_init(struct nvkm_subdev *subdev)
{
- struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev);
- struct nvkm_subdev *subdev = &engine->subdev;
+ struct nvkm_engine *engine = nvkm_engine(subdev);
struct nvkm_fb *fb = subdev->device->fb;
int ret = 0, i;
s64 time;
return ret;
}
- if (engine->subdev.object.oclass)
- return engine->subdev.object.oclass->ofuncs->init(&engine->subdev.object);
-
if (engine->func->oneinit && !engine->subdev.oneinit) {
nvkm_trace(subdev, "one-time init running...\n");
time = ktime_to_us(ktime_get());
}
static void *
-nvkm_engine_dtor(struct nvkm_subdev *obj)
+nvkm_engine_dtor(struct nvkm_subdev *subdev)
{
- struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev);
- if (engine->subdev.object.oclass) {
- engine->subdev.object.oclass->ofuncs->dtor(&engine->subdev.object);
- return NULL;
- }
+ struct nvkm_engine *engine = nvkm_engine(subdev);
if (engine->func->dtor)
return engine->func->dtor(engine);
return engine;
return nvkm_engine_ctor(func, device, index, pmc_enable,
enable, *pengine);
}
-
-struct nvkm_engine *
-nvkm_engine(void *obj, int idx)
-{
- obj = nvkm_subdev(obj, idx);
- if (obj && nv_iclass(obj, NV_ENGINE_CLASS))
- return nv_engine(obj);
- return NULL;
-}
-
-int
-nvkm_engine_create_(struct nvkm_object *parent, struct nvkm_object *engobj,
- struct nvkm_oclass *oclass, bool enable,
- const char *iname, const char *fname,
- int length, void **pobject)
-{
- struct nvkm_engine *engine;
- int ret;
-
- ret = nvkm_subdev_create_(parent, engobj, oclass, NV_ENGINE_CLASS,
- iname, fname, length, pobject);
- engine = *pobject;
- if (ret)
- return ret;
-
- if (parent) {
- struct nvkm_device *device = nv_device(parent);
- int engidx = nv_engidx(engine);
-
- if (device->disable_mask & (1ULL << engidx)) {
- if (!nvkm_boolopt(device->cfgopt, iname, false)) {
- nvkm_debug(&engine->subdev,
- "engine disabled by hw/fw\n");
- return -ENODEV;
- }
-
- nvkm_warn(&engine->subdev,
- "ignoring hw/fw engine disable\n");
- }
-
- if (!nvkm_boolopt(device->cfgopt, iname, enable)) {
- if (!enable)
- nvkm_warn(&engine->subdev,
- "disabled, %s=1 to enable\n", iname);
- return -ENODEV;
- }
- }
-
- INIT_LIST_HEAD(&engine->contexts);
- spin_lock_init(&engine->lock);
- engine->subdev.func = &nvkm_engine_func;
- return 0;
-}
return ret;
}
-void
-nvkm_gpuobj_destroy(struct nvkm_gpuobj *gpuobj)
-{
- if (gpuobj->node)
- nvkm_mm_free(&gpuobj->parent->heap, &gpuobj->node);
-
- gpuobj->heap.block_size = 1;
- nvkm_mm_fini(&gpuobj->heap);
-
- nvkm_memory_del(&gpuobj->memory);
- nvkm_object_destroy(&gpuobj->object);
-}
-
-#include <engine/fifo/chan.h>
-
-int
-nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, u32 pclass,
- struct nvkm_object *objgpu, u32 size, u32 align, u32 flags,
- int length, void **pobject)
-{
- struct nvkm_device *device = nv_device(parent);
- struct nvkm_gpuobj *pargpu = NULL;
- struct nvkm_gpuobj *gpuobj;
- struct nvkm_object *object = objgpu;
- const bool zero = (flags & NVOBJ_FLAG_ZERO_ALLOC);
- int ret;
-
- *pobject = NULL;
-
- while (object && object->func != &nvkm_fifo_chan_func)
- object = object->parent;
-
- if (object) {
- struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object);
- pargpu = chan->inst;
- } else
- if (objgpu) {
- while ((objgpu = nv_pclass(objgpu, NV_GPUOBJ_CLASS))) {
- if (nv_gpuobj(objgpu)->heap.block_size)
- break;
- objgpu = objgpu->parent;
- }
-
- if (WARN_ON(objgpu == NULL))
- return -EINVAL;
- pargpu = nv_gpuobj(objgpu);
- }
-
- ret = nvkm_object_create_(parent, engine, oclass, pclass |
- NV_GPUOBJ_CLASS, length, pobject);
- gpuobj = *pobject;
- if (ret)
- return ret;
-
- ret = nvkm_gpuobj_ctor(device, size, align, zero, pargpu, gpuobj);
- if (!(flags & NVOBJ_FLAG_HEAP))
- gpuobj->heap.block_size = 0;
- return ret;
-}
-
-void
-_nvkm_gpuobj_dtor(struct nvkm_object *object)
-{
- nvkm_gpuobj_destroy(nv_gpuobj(object));
-}
-
-int
-_nvkm_gpuobj_init(struct nvkm_object *object)
-{
- return nvkm_gpuobj_init(nv_gpuobj(object));
-}
-
-int
-_nvkm_gpuobj_fini(struct nvkm_object *object, bool suspend)
-{
- return nvkm_gpuobj_fini(nv_gpuobj(object), suspend);
-}
-
-u32
-_nvkm_gpuobj_rd32(struct nvkm_object *object, u64 addr)
-{
- struct nvkm_gpuobj *gpuobj = nv_gpuobj(object);
- return nvkm_ro32(gpuobj, addr);
-}
-
-void
-_nvkm_gpuobj_wr32(struct nvkm_object *object, u64 addr, u32 data)
-{
- struct nvkm_gpuobj *gpuobj = nv_gpuobj(object);
- nvkm_wo32(gpuobj, addr, data);
-}
-
int
nvkm_gpuobj_map(struct nvkm_gpuobj *gpuobj, struct nvkm_vm *vm,
u32 access, struct nvkm_vma *vma)
int
nvkm_object_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
- if (object->oclass) {
- if (object->oclass->ofuncs->mthd)
- return object->oclass->ofuncs->mthd(object, mthd, data, size);
- return -ENODEV;
- }
if (likely(object->func->mthd))
return object->func->mthd(object, mthd, data, size);
return -ENODEV;
nvkm_object_ntfy(struct nvkm_object *object, u32 mthd,
struct nvkm_event **pevent)
{
- if (object->oclass) {
- if (object->oclass->ofuncs->ntfy)
- return object->oclass->ofuncs->ntfy(object, mthd, pevent);
- return -ENODEV;
- }
if (likely(object->func->ntfy))
return object->func->ntfy(object, mthd, pevent);
return -ENODEV;
int
nvkm_object_map(struct nvkm_object *object, u64 *addr, u32 *size)
{
- if (object->oclass) {
- if (object->oclass->ofuncs->map)
- return object->oclass->ofuncs->map(object, addr, size);
- return -ENODEV;
- }
if (likely(object->func->map))
return object->func->map(object, addr, size);
return -ENODEV;
int
nvkm_object_rd08(struct nvkm_object *object, u64 addr, u8 *data)
{
- if (object->oclass) {
- if (object->oclass->ofuncs->rd08) {
- *data = object->oclass->ofuncs->rd08(object, addr);
- return 0;
- }
- *data = 0x00;
- return -ENODEV;
- }
if (likely(object->func->rd08))
return object->func->rd08(object, addr, data);
return -ENODEV;
int
nvkm_object_rd16(struct nvkm_object *object, u64 addr, u16 *data)
{
- if (object->oclass) {
- if (object->oclass->ofuncs->rd16) {
- *data = object->oclass->ofuncs->rd16(object, addr);
- return 0;
- }
- *data = 0x0000;
- return -ENODEV;
- }
if (likely(object->func->rd16))
return object->func->rd16(object, addr, data);
return -ENODEV;
int
nvkm_object_rd32(struct nvkm_object *object, u64 addr, u32 *data)
{
- if (object->oclass) {
- if (object->oclass->ofuncs->rd32) {
- *data = object->oclass->ofuncs->rd32(object, addr);
- return 0;
- }
- *data = 0x00000000;
- return -ENODEV;
- }
if (likely(object->func->rd32))
return object->func->rd32(object, addr, data);
return -ENODEV;
int
nvkm_object_wr08(struct nvkm_object *object, u64 addr, u8 data)
{
- if (object->oclass) {
- if (object->oclass->ofuncs->wr08) {
- object->oclass->ofuncs->wr08(object, addr, data);
- return 0;
- }
- return -ENODEV;
- }
if (likely(object->func->wr08))
return object->func->wr08(object, addr, data);
return -ENODEV;
int
nvkm_object_wr16(struct nvkm_object *object, u64 addr, u16 data)
{
- if (object->oclass) {
- if (object->oclass->ofuncs->wr16) {
- object->oclass->ofuncs->wr16(object, addr, data);
- return 0;
- }
- return -ENODEV;
- }
if (likely(object->func->wr16))
return object->func->wr16(object, addr, data);
return -ENODEV;
int
nvkm_object_wr32(struct nvkm_object *object, u64 addr, u32 data)
{
- if (object->oclass) {
- if (object->oclass->ofuncs->wr32) {
- object->oclass->ofuncs->wr32(object, addr, data);
- return 0;
- }
- return -ENODEV;
- }
if (likely(object->func->wr32))
return object->func->wr32(object, addr, data);
return -ENODEV;
nvkm_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *gpuobj,
int align, struct nvkm_gpuobj **pgpuobj)
{
- if (object->oclass)
- return -ENODEV;
if (object->func->bind)
return object->func->bind(object, gpuobj, align, pgpuobj);
return -ENODEV;
int
nvkm_object_fini(struct nvkm_object *object, bool suspend)
{
- if (object->oclass)
- return object->oclass->ofuncs->fini(object, suspend);
if (object->func->fini)
return object->func->fini(object, suspend);
return 0;
int
nvkm_object_init(struct nvkm_object *object)
{
- if (object->oclass)
- return object->oclass->ofuncs->init(object);
if (object->func->init)
return object->func->init(object);
return 0;
{
struct nvkm_object *object = *pobject;
- if (object && object->oclass) {
- object->oclass->ofuncs->dtor(object);
- return;
- }
-
if (object && !WARN_ON(!object->func)) {
if (object->func->dtor)
*pobject = object->func->dtor(object);
object->func = func;
object->client = oclass->client;
object->engine = nvkm_engine_ref(oclass->engine);
- object->oclass_name = oclass->base.oclass;
+ object->oclass = oclass->base.oclass;
object->handle = oclass->handle;
object->parent = oclass->parent;
atomic_set(&object->refcount, 1);
atomic_set(&object->usecount, 0);
-#ifdef NVKM_OBJECT_MAGIC
- object->_magic = NVKM_OBJECT_MAGIC;
-#endif
}
int
return nvkm_object_new_(func, oclass, data, size, pobject);
}
-int
-nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engobj,
- struct nvkm_oclass *oclass, u32 pclass,
- int size, void **pobject)
-{
- struct nvkm_engine *engine = engobj ? nv_engine(engobj) : NULL;
- struct nvkm_object *object;
-
- object = *pobject = kzalloc(size, GFP_KERNEL);
- if (!object)
- return -ENOMEM;
-
- nvkm_object_ref(parent, &object->parent);
- object->engine = nvkm_engine_ref(engine);
- object->oclass = oclass;
- object->pclass = pclass;
- atomic_set(&object->refcount, 1);
- atomic_set(&object->usecount, 0);
-
-#ifdef NVKM_OBJECT_MAGIC
- object->_magic = NVKM_OBJECT_MAGIC;
-#endif
- return 0;
-}
-
-int
-_nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
-{
- if (size != 0)
- return -ENOSYS;
- return nvkm_object_create(parent, engine, oclass, 0, pobject);
-}
-
-void
-nvkm_object_destroy(struct nvkm_object *object)
-{
- nvkm_engine_unref(&object->engine);
- nvkm_object_ref(NULL, &object->parent);
- kfree(object);
-}
-
-int
-_nvkm_object_init(struct nvkm_object *object)
-{
- return 0;
-}
-
-int
-_nvkm_object_fini(struct nvkm_object *object, bool suspend)
-{
- return 0;
-}
-
-struct nvkm_ofuncs
-nvkm_object_ofuncs = {
- .ctor = _nvkm_object_ctor,
- .dtor = nvkm_object_destroy,
- .init = _nvkm_object_init,
- .fini = _nvkm_object_fini,
-};
-
-int
-nvkm_object_old(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
-{
- struct nvkm_ofuncs *ofuncs = oclass->ofuncs;
- struct nvkm_object *object = NULL;
- int ret;
-
- ret = ofuncs->ctor(parent, engine, oclass, data, size, &object);
- *pobject = object;
- if (ret < 0) {
- if (object) {
- ofuncs->dtor(object);
- *pobject = NULL;
- }
-
- return ret;
- }
-
- if (ret == 0) {
- if (!nv_iclass(object, NV_SUBDEV_CLASS))
- atomic_set(&object->refcount, 1);
- }
-
- return 0;
-}
-
void
nvkm_object_ref(struct nvkm_object *obj, struct nvkm_object **ref)
{
{
struct nvkm_oproxy *oproxy = nvkm_oproxy(object);
oclass->parent = oproxy->object;
- if (oproxy->object->oclass)
- return -ENOSYS;
if (!oproxy->object->func->sclass)
return -ENODEV;
return oproxy->object->func->sclass(oproxy->object, index, oclass);
data->chid = chid;
data->handle = handle;
- if (!object) {
- inst = 0;
- goto done;
- }
-
- if (nv_iclass(object, NV_GPUOBJ_CLASS)) {
- struct nvkm_gpuobj *gpuobj = nv_gpuobj(object);
- if (ramht->device->card_type >= NV_50)
- inst = gpuobj->node->offset;
- else
- inst = gpuobj->addr;
- goto done;
- }
+ if (object) {
+ ret = nvkm_object_bind(object, ramht->parent, 16, &data->inst);
+ if (ret) {
+ if (ret != -ENODEV) {
+ data->chid = -1;
+ return ret;
+ }
+ data->inst = NULL;
+ }
- ret = nvkm_object_bind(object, ramht->parent, 16, &data->inst);
- if (ret) {
- if (ret != -ENODEV) {
- data->chid = -1;
- return ret;
+ if (data->inst) {
+ if (ramht->device->card_type >= NV_50)
+ inst = data->inst->node->offset;
+ else
+ inst = data->inst->addr;
}
- data->inst = NULL;
- }
- if (data->inst) {
- if (ramht->device->card_type >= NV_50)
- inst = data->inst->node->offset;
- else
- inst = data->inst->addr;
+ if (addr < 0) context |= inst << -addr;
+ else context |= inst >> addr;
}
-done:
- if (addr < 0) context |= inst << -addr;
- else context |= inst >> addr;
-
nvkm_kmap(ramht->gpuobj);
nvkm_wo32(ramht->gpuobj, (co << 3) + 0, handle);
nvkm_wo32(ramht->gpuobj, (co << 3) + 4, context);
#include <core/device.h>
#include <core/option.h>
-static struct lock_class_key nvkm_subdev_lock_class[NVDEV_SUBDEV_NR];
+static struct lock_class_key nvkm_subdev_lock_class[NVKM_SUBDEV_NR];
const char *
-nvkm_subdev_name[64] = {
- [NVDEV_SUBDEV_BAR ] = "bar",
- [NVDEV_SUBDEV_VBIOS ] = "bios",
- [NVDEV_SUBDEV_BUS ] = "bus",
- [NVDEV_SUBDEV_CLK ] = "clk",
- [NVDEV_SUBDEV_DEVINIT] = "devinit",
- [NVDEV_SUBDEV_FB ] = "fb",
- [NVDEV_SUBDEV_FUSE ] = "fuse",
- [NVDEV_SUBDEV_GPIO ] = "gpio",
- [NVDEV_SUBDEV_I2C ] = "i2c",
- [NVDEV_SUBDEV_IBUS ] = "priv",
- [NVDEV_SUBDEV_INSTMEM] = "imem",
- [NVDEV_SUBDEV_LTC ] = "ltc",
- [NVDEV_SUBDEV_MC ] = "mc",
- [NVDEV_SUBDEV_MMU ] = "mmu",
- [NVDEV_SUBDEV_MXM ] = "mxm",
- [NVDEV_SUBDEV_PMU ] = "pmu",
- [NVDEV_SUBDEV_THERM ] = "therm",
- [NVDEV_SUBDEV_TIMER ] = "tmr",
- [NVDEV_SUBDEV_VOLT ] = "volt",
- [NVDEV_ENGINE_BSP ] = "bsp",
- [NVDEV_ENGINE_CE0 ] = "ce0",
- [NVDEV_ENGINE_CE1 ] = "ce1",
- [NVDEV_ENGINE_CE2 ] = "ce2",
- [NVDEV_ENGINE_CIPHER ] = "cipher",
- [NVDEV_ENGINE_DISP ] = "disp",
- [NVDEV_ENGINE_DMAOBJ ] = "dma",
- [NVDEV_ENGINE_FIFO ] = "fifo",
- [NVDEV_ENGINE_GR ] = "gr",
- [NVDEV_ENGINE_IFB ] = "ifb",
- [NVDEV_ENGINE_ME ] = "me",
- [NVDEV_ENGINE_MPEG ] = "mpeg",
- [NVDEV_ENGINE_MSENC ] = "msenc",
- [NVDEV_ENGINE_MSPDEC ] = "mspdec",
- [NVDEV_ENGINE_MSPPP ] = "msppp",
- [NVDEV_ENGINE_MSVLD ] = "msvld",
- [NVDEV_ENGINE_PM ] = "pm",
- [NVDEV_ENGINE_SEC ] = "sec",
- [NVDEV_ENGINE_SW ] = "sw",
- [NVDEV_ENGINE_VIC ] = "vic",
- [NVDEV_ENGINE_VP ] = "vp",
+nvkm_subdev_name[NVKM_SUBDEV_NR] = {
+ [NVKM_SUBDEV_BAR ] = "bar",
+ [NVKM_SUBDEV_VBIOS ] = "bios",
+ [NVKM_SUBDEV_BUS ] = "bus",
+ [NVKM_SUBDEV_CLK ] = "clk",
+ [NVKM_SUBDEV_DEVINIT] = "devinit",
+ [NVKM_SUBDEV_FB ] = "fb",
+ [NVKM_SUBDEV_FUSE ] = "fuse",
+ [NVKM_SUBDEV_GPIO ] = "gpio",
+ [NVKM_SUBDEV_I2C ] = "i2c",
+ [NVKM_SUBDEV_IBUS ] = "priv",
+ [NVKM_SUBDEV_INSTMEM] = "imem",
+ [NVKM_SUBDEV_LTC ] = "ltc",
+ [NVKM_SUBDEV_MC ] = "mc",
+ [NVKM_SUBDEV_MMU ] = "mmu",
+ [NVKM_SUBDEV_MXM ] = "mxm",
+ [NVKM_SUBDEV_PMU ] = "pmu",
+ [NVKM_SUBDEV_THERM ] = "therm",
+ [NVKM_SUBDEV_TIMER ] = "tmr",
+ [NVKM_SUBDEV_VOLT ] = "volt",
+ [NVKM_ENGINE_BSP ] = "bsp",
+ [NVKM_ENGINE_CE0 ] = "ce0",
+ [NVKM_ENGINE_CE1 ] = "ce1",
+ [NVKM_ENGINE_CE2 ] = "ce2",
+ [NVKM_ENGINE_CIPHER ] = "cipher",
+ [NVKM_ENGINE_DISP ] = "disp",
+ [NVKM_ENGINE_DMAOBJ ] = "dma",
+ [NVKM_ENGINE_FIFO ] = "fifo",
+ [NVKM_ENGINE_GR ] = "gr",
+ [NVKM_ENGINE_IFB ] = "ifb",
+ [NVKM_ENGINE_ME ] = "me",
+ [NVKM_ENGINE_MPEG ] = "mpeg",
+ [NVKM_ENGINE_MSENC ] = "msenc",
+ [NVKM_ENGINE_MSPDEC ] = "mspdec",
+ [NVKM_ENGINE_MSPPP ] = "msppp",
+ [NVKM_ENGINE_MSVLD ] = "msvld",
+ [NVKM_ENGINE_PM ] = "pm",
+ [NVKM_ENGINE_SEC ] = "sec",
+ [NVKM_ENGINE_SW ] = "sw",
+ [NVKM_ENGINE_VIC ] = "vic",
+ [NVKM_ENGINE_VP ] = "vp",
};
void
nvkm_subdev_intr(struct nvkm_subdev *subdev)
{
- if (subdev->object.oclass) {
- if (subdev->intr)
- subdev->intr(subdev);
- return;
- }
-
if (subdev->func->intr)
subdev->func->intr(subdev);
}
const char *action = suspend ? "suspend" : "fini";
u32 pmc_enable = subdev->pmc_enable;
s64 time;
- int ret;
nvkm_trace(subdev, "%s running...\n", action);
time = ktime_to_us(ktime_get());
- if (!subdev->func) {
- ret = subdev->object.oclass->ofuncs->fini(&subdev->object, suspend);
- if (ret)
- return ret;
- goto done;
- }
-
if (subdev->func->fini) {
int ret = subdev->func->fini(subdev, suspend);
if (ret) {
nvkm_rd32(device, 0x000200);
}
-done:
time = ktime_to_us(ktime_get()) - time;
nvkm_trace(subdev, "%s completed in %lldus\n", action, time);
return 0;
nvkm_trace(subdev, "preinit running...\n");
time = ktime_to_us(ktime_get());
- if (!subdev->object.oclass && subdev->func->preinit) {
+ if (subdev->func->preinit) {
int ret = subdev->func->preinit(subdev);
if (ret) {
nvkm_error(subdev, "preinit failed, %d\n", ret);
nvkm_trace(subdev, "init running...\n");
time = ktime_to_us(ktime_get());
- if (!subdev->func) {
- ret = subdev->object.oclass->ofuncs->init(&subdev->object);
- if (ret)
- return ret;
- goto done;
- }
-
if (subdev->func->oneinit && !subdev->oneinit) {
s64 time;
nvkm_trace(subdev, "one-time init running...\n");
}
}
-done:
time = ktime_to_us(ktime_get()) - time;
nvkm_trace(subdev, "init completed in %lldus\n", time);
return 0;
struct nvkm_subdev *subdev = *psubdev;
s64 time;
- if (subdev && subdev->object.oclass) {
- subdev->object.oclass->ofuncs->dtor(&subdev->object);
- return;
- }
-
if (subdev && !WARN_ON(!subdev->func)) {
nvkm_trace(subdev, "destroy running...\n");
time = ktime_to_us(ktime_get());
}
}
-static const struct nvkm_object_func
-nvkm_subdev_func = {
-};
-
void
nvkm_subdev_ctor(const struct nvkm_subdev_func *func,
struct nvkm_device *device, int index, u32 pmc_enable,
struct nvkm_subdev *subdev)
{
const char *name = nvkm_subdev_name[index];
- struct nvkm_oclass hack = {};
- nvkm_object_ctor(&nvkm_subdev_func, &hack, &subdev->object);
subdev->func = func;
subdev->device = device;
subdev->index = index;
__mutex_init(&subdev->mutex, name, &nvkm_subdev_lock_class[index]);
subdev->debug = nvkm_dbgopt(device->dbgopt, name);
}
-
-struct nvkm_subdev *
-nvkm_subdev(void *obj, int idx)
-{
- struct nvkm_object *object = nv_object(obj);
- while (object && !nv_iclass(object, NV_SUBDEV_CLASS))
- object = object->parent;
- if (object == NULL || !object->parent || nv_subidx(nv_subdev(object)) != idx) {
- struct nvkm_device *device = nv_device(obj);
- return nvkm_device_subdev(device, idx);
- }
- return object ? nv_subdev(object) : NULL;
-}
-
-void
-nvkm_subdev_reset(struct nvkm_object *obj)
-{
- struct nvkm_subdev *subdev = container_of(obj, typeof(*subdev), object);
- nvkm_trace(subdev, "resetting...\n");
- nvkm_object_fini(&subdev->object, false);
- nvkm_trace(subdev, "reset\n");
-}
-
-int
-nvkm_subdev_init_old(struct nvkm_subdev *subdev)
-{
- int ret = _nvkm_object_init(&subdev->object);
- if (ret)
- return ret;
-
- nvkm_subdev_reset(&subdev->object);
- return 0;
-}
-
-int
-_nvkm_subdev_init(struct nvkm_object *object)
-{
- struct nvkm_subdev *subdev = (void *)object;
- return nvkm_subdev_init_old(subdev);
-}
-
-int
-nvkm_subdev_fini_old(struct nvkm_subdev *subdev, bool suspend)
-{
- struct nvkm_device *device = subdev->device;
-
- if (subdev->unit) {
- nvkm_mask(device, 0x000200, subdev->unit, 0x00000000);
- nvkm_mask(device, 0x000200, subdev->unit, subdev->unit);
- }
-
- return _nvkm_object_fini(&subdev->object, suspend);
-}
-
-int
-_nvkm_subdev_fini(struct nvkm_object *object, bool suspend)
-{
- struct nvkm_subdev *subdev = (void *)object;
- return nvkm_subdev_fini_old(subdev, suspend);
-}
-
-void
-nvkm_subdev_destroy(struct nvkm_subdev *subdev)
-{
- nvkm_object_destroy(&subdev->object);
-}
-
-void
-_nvkm_subdev_dtor(struct nvkm_object *object)
-{
- nvkm_subdev_destroy(nv_subdev(object));
-}
-
-int
-nvkm_subdev_create_(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, u32 pclass,
- const char *subname, const char *sysname,
- int size, void **pobject)
-{
- const int subidx = oclass->handle & 0xff;
- const char *name = nvkm_subdev_name[subidx];
- struct nvkm_subdev *subdev;
- int ret;
-
- ret = nvkm_object_create_(parent, engine, oclass, pclass |
- NV_SUBDEV_CLASS, size, pobject);
- subdev = *pobject;
- if (ret)
- return ret;
-
- __mutex_init(&subdev->mutex, name, &nvkm_subdev_lock_class[subidx]);
- subdev->index = subidx;
-
- if (parent) {
- struct nvkm_device *device = nv_device(parent);
- subdev->debug = nvkm_dbgopt(device->dbgopt, name);
- subdev->device = device;
- } else {
- subdev->device = nv_device(subdev);
- }
-
- return 0;
-}
gf100_ce_init(struct nvkm_falcon *ce)
{
struct nvkm_device *device = ce->engine.subdev.device;
- const int index = ce->engine.subdev.index - NVDEV_ENGINE_CE0;
+ const int index = ce->engine.subdev.index - NVKM_ENGINE_CE0;
nvkm_wr32(device, ce->addr + 0x084, index);
}
gf100_ce_new(struct nvkm_device *device, int index,
struct nvkm_engine **pengine)
{
- if (index == NVDEV_ENGINE_CE0) {
+ if (index == NVKM_ENGINE_CE0) {
return nvkm_falcon_new_(&gf100_ce0, device, index, true,
0x104000, pengine);
} else
- if (index == NVDEV_ENGINE_CE1) {
+ if (index == NVKM_ENGINE_CE1) {
return nvkm_falcon_new_(&gf100_ce1, device, index, true,
0x105000, pengine);
}
void
gk104_ce_intr(struct nvkm_engine *ce)
{
- const u32 base = (ce->subdev.index - NVDEV_ENGINE_CE0) * 0x1000;
+ const u32 base = (ce->subdev.index - NVKM_ENGINE_CE0) * 0x1000;
struct nvkm_subdev *subdev = &ce->subdev;
struct nvkm_device *device = subdev->device;
u32 stat = nvkm_rd32(device, 0x104908 + base);
gk104_ce_new(struct nvkm_device *device, int index,
struct nvkm_engine **pengine)
{
- if (index == NVDEV_ENGINE_CE0) {
+ if (index == NVKM_ENGINE_CE0) {
return nvkm_engine_new_(&gk104_ce, device, index,
0x00000040, true, pengine);
} else
- if (index == NVDEV_ENGINE_CE1) {
+ if (index == NVKM_ENGINE_CE1) {
return nvkm_engine_new_(&gk104_ce, device, index,
0x00000080, true, pengine);
} else
- if (index == NVDEV_ENGINE_CE2) {
+ if (index == NVKM_ENGINE_CE2) {
return nvkm_engine_new_(&gk104_ce, device, index,
0x00200000, true, pengine);
}
gm204_ce_new(struct nvkm_device *device, int index,
struct nvkm_engine **pengine)
{
- if (index == NVDEV_ENGINE_CE0) {
+ if (index == NVKM_ENGINE_CE0) {
return nvkm_engine_new_(&gm204_ce, device, index,
0x00000040, true, pengine);
} else
- if (index == NVDEV_ENGINE_CE1) {
+ if (index == NVKM_ENGINE_CE1) {
return nvkm_engine_new_(&gm204_ce, device, index,
0x00000080, true, pengine);
} else
- if (index == NVDEV_ENGINE_CE2) {
+ if (index == NVKM_ENGINE_CE2) {
return nvkm_engine_new_(&gm204_ce, device, index,
0x00200000, true, pengine);
}
{
struct nvkm_subdev *subdev = &ce->engine.subdev;
struct nvkm_device *device = subdev->device;
- const u32 base = (subdev->index - NVDEV_ENGINE_CE0) * 0x1000;
+ const u32 base = (subdev->index - NVKM_ENGINE_CE0) * 0x1000;
u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff;
u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16;
u32 mthd = (addr & 0x07ff) << 2;
align, false, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
- nvkm_wo32(*pgpuobj, 0x00, object->oclass_name);
+ nvkm_wo32(*pgpuobj, 0x00, object->oclass);
nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
nvkm-y += nvkm/engine/device/pci.o
nvkm-y += nvkm/engine/device/tegra.o
nvkm-y += nvkm/engine/device/user.o
-
-nvkm-y += nvkm/engine/device/nv04.o
-nvkm-y += nvkm/engine/device/nv10.o
-nvkm-y += nvkm/engine/device/nv20.o
-nvkm-y += nvkm/engine/device/nv30.o
-nvkm-y += nvkm/engine/device/nv40.o
-nvkm-y += nvkm/engine/device/nv50.o
-nvkm-y += nvkm/engine/device/gf100.o
-nvkm-y += nvkm/engine/device/gk104.o
-nvkm-y += nvkm/engine/device/gm100.o
.sw = gf100_sw_new,
};
-#include <core/client.h>
-
-struct nvkm_device *
-nv_device(void *obj)
-{
- struct nvkm_object *device = nv_object(obj);
-
- if (device->engine == NULL) {
- while (device && device->parent) {
- if (!nv_iclass(device, NV_SUBDEV_CLASS) &&
- device->parent == &nvkm_client(device)->object) {
- struct {
- struct nvkm_object base;
- struct nvkm_device *device;
- } *udevice = (void *)device;
- return udevice->device;
- }
- device = device->parent;
- }
- } else {
- device = &nv_object(obj)->engine->subdev.object;
- if (device && device->parent)
- device = device->parent;
- }
-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
- BUG_ON(!device);
-#endif
- return (void *)device;
-}
-
static int
nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size,
struct nvkm_notify *notify)
return NULL;
switch (index) {
-#define _(n,p,m) case NVDEV_SUBDEV_##n: if (p) return (m); break
+#define _(n,p,m) case NVKM_SUBDEV_##n: if (p) return (m); break
_(BAR , device->bar , &device->bar->subdev);
_(VBIOS , device->bios , &device->bios->subdev);
_(BUS , device->bus , &device->bus->subdev);
return NULL;
switch (index) {
-#define _(n,p,m) case NVDEV_ENGINE_##n: if (p) return (m); break
+#define _(n,p,m) case NVKM_ENGINE_##n: if (p) return (m); break
_(BSP , device->bsp , device->bsp);
_(CE0 , device->ce[0] , device->ce[0]);
_(CE1 , device->ce[1] , device->ce[1]);
nvkm_acpi_fini(device);
- for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
+ for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) {
if ((subdev = nvkm_device_subdev(device, i))) {
ret = nvkm_subdev_fini(subdev, suspend);
if (ret && suspend)
if (rret)
nvkm_fatal(subdev, "failed restart, %d\n", ret);
}
- } while (++i < NVDEV_SUBDEV_NR);
+ } while (++i < NVKM_SUBDEV_NR);
nvdev_trace(device, "%s failed with %d\n", action, ret);
return ret;
goto fail;
}
- for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
+ for (i = 0; i < NVKM_SUBDEV_NR; i++) {
if ((subdev = nvkm_device_subdev(device, i))) {
ret = nvkm_subdev_preinit(subdev);
if (ret)
nvkm_device_init(struct nvkm_device *device)
{
struct nvkm_subdev *subdev;
- int ret, i = 0, c;
+ int ret, i;
s64 time;
ret = nvkm_device_preinit(device);
nvdev_trace(device, "init running...\n");
time = ktime_to_us(ktime_get());
- for (i = 0, c = 0; i < NVDEV_SUBDEV_NR; i++) {
-#define _(s,m) case s: if (device->oclass[s] && !device->m) { \
- ret = nvkm_object_old(nv_object(device), NULL, \
- device->oclass[s], NULL, (s), \
- (struct nvkm_object **)&device->m); \
- if (ret == -ENODEV) { \
- device->oclass[s] = NULL; \
- continue; \
- } \
- if (ret) \
- goto fail; \
-} break
- switch (i) {
- _(NVDEV_SUBDEV_BAR , bar);
- _(NVDEV_SUBDEV_VBIOS , bios);
- _(NVDEV_SUBDEV_BUS , bus);
- _(NVDEV_SUBDEV_CLK , clk);
- _(NVDEV_SUBDEV_DEVINIT, devinit);
- _(NVDEV_SUBDEV_FB , fb);
- _(NVDEV_SUBDEV_FUSE , fuse);
- _(NVDEV_SUBDEV_GPIO , gpio);
- _(NVDEV_SUBDEV_I2C , i2c);
- _(NVDEV_SUBDEV_IBUS , ibus);
- _(NVDEV_SUBDEV_INSTMEM, imem);
- _(NVDEV_SUBDEV_LTC , ltc);
- _(NVDEV_SUBDEV_MC , mc);
- _(NVDEV_SUBDEV_MMU , mmu);
- _(NVDEV_SUBDEV_MXM , mxm);
- _(NVDEV_SUBDEV_PMU , pmu);
- _(NVDEV_SUBDEV_THERM , therm);
- _(NVDEV_SUBDEV_TIMER , timer);
- _(NVDEV_SUBDEV_VOLT , volt);
- _(NVDEV_ENGINE_BSP , bsp);
- _(NVDEV_ENGINE_CE0 , ce[0]);
- _(NVDEV_ENGINE_CE1 , ce[1]);
- _(NVDEV_ENGINE_CE2 , ce[2]);
- _(NVDEV_ENGINE_CIPHER , cipher);
- _(NVDEV_ENGINE_DISP , disp);
- _(NVDEV_ENGINE_DMAOBJ , dma);
- _(NVDEV_ENGINE_FIFO , fifo);
- _(NVDEV_ENGINE_GR , gr);
- _(NVDEV_ENGINE_IFB , ifb);
- _(NVDEV_ENGINE_ME , me);
- _(NVDEV_ENGINE_MPEG , mpeg);
- _(NVDEV_ENGINE_MSENC , msenc);
- _(NVDEV_ENGINE_MSPDEC , mspdec);
- _(NVDEV_ENGINE_MSPPP , msppp);
- _(NVDEV_ENGINE_MSVLD , msvld);
- _(NVDEV_ENGINE_PM , pm);
- _(NVDEV_ENGINE_SEC , sec);
- _(NVDEV_ENGINE_SW , sw);
- _(NVDEV_ENGINE_VIC , vic);
- _(NVDEV_ENGINE_VP , vp);
- default:
- WARN_ON(1);
- continue;
- }
-#undef _
-
- /* note: can't init *any* subdevs until devinit has been run
- * due to not knowing exactly what the vbios init tables will
- * mess with. devinit also can't be run until all of its
- * dependencies have been created.
- *
- * this code delays init of any subdev until all of devinit's
- * dependencies have been created, and then initialises each
- * subdev in turn as they're created.
- */
- while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) {
- if ((subdev = nvkm_device_subdev(device, c++))) {
- ret = nvkm_subdev_init(subdev);
- if (ret)
- goto fail;
- }
+ for (i = 0; i < NVKM_SUBDEV_NR; i++) {
+ if ((subdev = nvkm_device_subdev(device, i))) {
+ ret = nvkm_subdev_init(subdev);
+ if (ret)
+ goto fail;
}
}
if (device) {
mutex_lock(&nv_devices_mutex);
device->disable_mask = 0;
- for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
+ for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) {
struct nvkm_subdev *subdev =
nvkm_device_subdev(device, i);
nvkm_subdev_del(&subdev);
}
}
-static const struct nvkm_engine_func
-nvkm_device_func = {
-};
-
int
nvkm_device_ctor(const struct nvkm_device_func *func,
const struct nvkm_device_quirk *quirk,
device->dbgopt = dbg;
device->name = name;
list_add_tail(&device->head, &nv_devices);
-
- ret = nvkm_engine_ctor(&nvkm_device_func, device, 0, 0,
- true, &device->engine);
- device->engine.subdev.object.parent = NULL;
- if (ret)
- goto done;
+ device->debug = nvkm_dbgopt(device->dbgopt, "device");
ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event);
if (ret)
device->card_type = NV_04;
}
- switch (device->card_type) {
- case NV_04: ret = nv04_identify(device); break;
- case NV_10:
- case NV_11: ret = nv10_identify(device); break;
- case NV_20: ret = nv20_identify(device); break;
- case NV_30: ret = nv30_identify(device); break;
- case NV_40: ret = nv40_identify(device); break;
- case NV_50: ret = nv50_identify(device); break;
- case NV_C0: ret = gf100_identify(device); break;
- case NV_E0: ret = gk104_identify(device); break;
- case GM100: ret = gm100_identify(device); break;
- default:
- ret = -EINVAL;
- break;
- }
-
- switch (!ret * device->chipset) {
+ switch (device->chipset) {
case 0x004: device->chip = &nv4_chipset; break;
case 0x005: device->chip = &nv5_chipset; break;
case 0x010: device->chip = &nv10_chipset; break;
}
}
- /* disable subdevs that aren't required (used by tools) */
- for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
- if (!(subdev_mask & (1ULL << i)))
- device->oclass[i] = NULL;
- }
-
- atomic_set(&device->engine.subdev.object.usecount, 2);
mutex_init(&device->mutex);
- for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
+ for (i = 0; i < NVKM_SUBDEV_NR; i++) {
#define _(s,m) case s: \
if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \
ret = device->chip->m(device, (s), &device->m); \
} \
break
switch (i) {
- _(NVDEV_SUBDEV_BAR , bar);
- _(NVDEV_SUBDEV_VBIOS , bios);
- _(NVDEV_SUBDEV_BUS , bus);
- _(NVDEV_SUBDEV_CLK , clk);
- _(NVDEV_SUBDEV_DEVINIT, devinit);
- _(NVDEV_SUBDEV_FB , fb);
- _(NVDEV_SUBDEV_FUSE , fuse);
- _(NVDEV_SUBDEV_GPIO , gpio);
- _(NVDEV_SUBDEV_I2C , i2c);
- _(NVDEV_SUBDEV_IBUS , ibus);
- _(NVDEV_SUBDEV_INSTMEM, imem);
- _(NVDEV_SUBDEV_LTC , ltc);
- _(NVDEV_SUBDEV_MC , mc);
- _(NVDEV_SUBDEV_MMU , mmu);
- _(NVDEV_SUBDEV_MXM , mxm);
- _(NVDEV_SUBDEV_PMU , pmu);
- _(NVDEV_SUBDEV_THERM , therm);
- _(NVDEV_SUBDEV_TIMER , timer);
- _(NVDEV_SUBDEV_VOLT , volt);
- _(NVDEV_ENGINE_BSP , bsp);
- _(NVDEV_ENGINE_CE0 , ce[0]);
- _(NVDEV_ENGINE_CE1 , ce[1]);
- _(NVDEV_ENGINE_CE2 , ce[2]);
- _(NVDEV_ENGINE_CIPHER , cipher);
- _(NVDEV_ENGINE_DISP , disp);
- _(NVDEV_ENGINE_DMAOBJ , dma);
- _(NVDEV_ENGINE_FIFO , fifo);
- _(NVDEV_ENGINE_GR , gr);
- _(NVDEV_ENGINE_IFB , ifb);
- _(NVDEV_ENGINE_ME , me);
- _(NVDEV_ENGINE_MPEG , mpeg);
- _(NVDEV_ENGINE_MSENC , msenc);
- _(NVDEV_ENGINE_MSPDEC , mspdec);
- _(NVDEV_ENGINE_MSPPP , msppp);
- _(NVDEV_ENGINE_MSVLD , msvld);
- _(NVDEV_ENGINE_PM , pm);
- _(NVDEV_ENGINE_SEC , sec);
- _(NVDEV_ENGINE_SW , sw);
- _(NVDEV_ENGINE_VIC , vic);
- _(NVDEV_ENGINE_VP , vp);
+ _(NVKM_SUBDEV_BAR , bar);
+ _(NVKM_SUBDEV_VBIOS , bios);
+ _(NVKM_SUBDEV_BUS , bus);
+ _(NVKM_SUBDEV_CLK , clk);
+ _(NVKM_SUBDEV_DEVINIT, devinit);
+ _(NVKM_SUBDEV_FB , fb);
+ _(NVKM_SUBDEV_FUSE , fuse);
+ _(NVKM_SUBDEV_GPIO , gpio);
+ _(NVKM_SUBDEV_I2C , i2c);
+ _(NVKM_SUBDEV_IBUS , ibus);
+ _(NVKM_SUBDEV_INSTMEM, imem);
+ _(NVKM_SUBDEV_LTC , ltc);
+ _(NVKM_SUBDEV_MC , mc);
+ _(NVKM_SUBDEV_MMU , mmu);
+ _(NVKM_SUBDEV_MXM , mxm);
+ _(NVKM_SUBDEV_PMU , pmu);
+ _(NVKM_SUBDEV_THERM , therm);
+ _(NVKM_SUBDEV_TIMER , timer);
+ _(NVKM_SUBDEV_VOLT , volt);
+ _(NVKM_ENGINE_BSP , bsp);
+ _(NVKM_ENGINE_CE0 , ce[0]);
+ _(NVKM_ENGINE_CE1 , ce[1]);
+ _(NVKM_ENGINE_CE2 , ce[2]);
+ _(NVKM_ENGINE_CIPHER , cipher);
+ _(NVKM_ENGINE_DISP , disp);
+ _(NVKM_ENGINE_DMAOBJ , dma);
+ _(NVKM_ENGINE_FIFO , fifo);
+ _(NVKM_ENGINE_GR , gr);
+ _(NVKM_ENGINE_IFB , ifb);
+ _(NVKM_ENGINE_ME , me);
+ _(NVKM_ENGINE_MPEG , mpeg);
+ _(NVKM_ENGINE_MSENC , msenc);
+ _(NVKM_ENGINE_MSPDEC , mspdec);
+ _(NVKM_ENGINE_MSPPP , msppp);
+ _(NVKM_ENGINE_MSVLD , msvld);
+ _(NVKM_ENGINE_PM , pm);
+ _(NVKM_ENGINE_SEC , sec);
+ _(NVKM_ENGINE_SW , sw);
+ _(NVKM_ENGINE_VIC , vic);
+ _(NVKM_ENGINE_VP , vp);
default:
WARN_ON(1);
continue;
+++ /dev/null
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-#include "priv.h"
-
-int
-gf100_identify(struct nvkm_device *device)
-{
- switch (device->chipset) {
- case 0xc0:
- break;
- case 0xc4:
- break;
- case 0xc3:
- break;
- case 0xce:
- break;
- case 0xcf:
- break;
- case 0xc1:
- break;
- case 0xc8:
- break;
- case 0xd9:
- break;
- case 0xd7:
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-#include "priv.h"
-
-int
-gk104_identify(struct nvkm_device *device)
-{
- switch (device->chipset) {
- case 0xe4:
- break;
- case 0xe7:
- break;
- case 0xe6:
- break;
- case 0xea:
- break;
- case 0xf0:
- break;
- case 0xf1:
- break;
- case 0x106:
- break;
- case 0x108:
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-#include "priv.h"
-
-int
-gm100_identify(struct nvkm_device *device)
-{
- switch (device->chipset) {
- case 0x117:
-
-#if 0
-#endif
-#if 0
-#endif
-#if 0
-#endif
- break;
- case 0x124:
-#if 0
- /* looks to be some non-trivial changes */
- /* priv ring says no to 0x10eb14 writes */
-#endif
-#if 0
-#endif
-#if 0
-#endif
- break;
- case 0x126:
-#if 0
- /* looks to be some non-trivial changes */
- /* priv ring says no to 0x10eb14 writes */
-#endif
-#if 0
-#endif
-#if 0
-#endif
- break;
- case 0x12b:
-
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-#include "priv.h"
-
-int
-nv04_identify(struct nvkm_device *device)
-{
- switch (device->chipset) {
- case 0x04:
- break;
- case 0x05:
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-#include "priv.h"
-
-int
-nv10_identify(struct nvkm_device *device)
-{
- switch (device->chipset) {
- case 0x10:
- break;
- case 0x15:
- break;
- case 0x16:
- break;
- case 0x1a:
- break;
- case 0x11:
- break;
- case 0x17:
- break;
- case 0x1f:
- break;
- case 0x18:
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-#include "priv.h"
-
-int
-nv20_identify(struct nvkm_device *device)
-{
- switch (device->chipset) {
- case 0x20:
- break;
- case 0x25:
- break;
- case 0x28:
- break;
- case 0x2a:
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-#include "priv.h"
-
-int
-nv30_identify(struct nvkm_device *device)
-{
- switch (device->chipset) {
- case 0x30:
- break;
- case 0x35:
- break;
- case 0x31:
- break;
- case 0x36:
- break;
- case 0x34:
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-#include "priv.h"
-
-int
-nv40_identify(struct nvkm_device *device)
-{
- switch (device->chipset) {
- case 0x40:
- break;
- case 0x41:
- break;
- case 0x42:
- break;
- case 0x43:
- break;
- case 0x45:
- break;
- case 0x47:
- break;
- case 0x49:
- break;
- case 0x4b:
- break;
- case 0x44:
- break;
- case 0x46:
- break;
- case 0x4a:
- break;
- case 0x4c:
- break;
- case 0x4e:
- break;
- case 0x63:
- break;
- case 0x67:
- break;
- case 0x68:
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-#include "priv.h"
-
-int
-nv50_identify(struct nvkm_device *device)
-{
- switch (device->chipset) {
- case 0x50:
- break;
- case 0x84:
- break;
- case 0x86:
- break;
- case 0x92:
- break;
- case 0x94:
- break;
- case 0x96:
- break;
- case 0x98:
- break;
- case 0xa0:
- break;
- case 0xaa:
- break;
- case 0xac:
- break;
- case 0xa3:
- break;
- case 0xa5:
- break;
- case 0xa8:
- break;
- case 0xaf:
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
struct nvkm_device *);
int nvkm_device_init(struct nvkm_device *);
int nvkm_device_fini(struct nvkm_device *, bool suspend);
-
-int nv04_identify(struct nvkm_device *);
-int nv10_identify(struct nvkm_device *);
-int nv20_identify(struct nvkm_device *);
-int nv30_identify(struct nvkm_device *);
-int nv40_identify(struct nvkm_device *);
-int nv50_identify(struct nvkm_device *);
-int gf100_identify(struct nvkm_device *);
-int gk104_identify(struct nvkm_device *);
-int gm100_identify(struct nvkm_device *);
#endif
struct nvkm_udevice *udev = nvkm_udevice(object);
struct nvkm_device *device = udev->device;
struct nvkm_engine *engine;
- u64 mask = (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_FIFO) |
- (1ULL << NVDEV_ENGINE_DISP) |
- (1ULL << NVDEV_ENGINE_PM);
+ u64 mask = (1ULL << NVKM_ENGINE_DMAOBJ) |
+ (1ULL << NVKM_ENGINE_FIFO) |
+ (1ULL << NVKM_ENGINE_DISP) |
+ (1ULL << NVKM_ENGINE_PM);
const struct nvkm_device_oclass *sclass = NULL;
int i;
struct nvkm_device *device = disp->base.engine.subdev.device;
const struct nvkm_device_oclass *oclass = NULL;
- sclass->engine = nvkm_device_engine(device, NVDEV_ENGINE_DMAOBJ);
+ sclass->engine = nvkm_device_engine(device, NVKM_ENGINE_DMAOBJ);
if (sclass->engine && sclass->engine->func->base.sclass) {
sclass->engine->func->base.sclass(sclass, index, &oclass);
if (oclass) {
return data;
}
-const struct nvkm_object_func
+static const struct nvkm_object_func
nvkm_fifo_chan_func = {
.dtor = nvkm_fifo_chan_dtor,
.init = nvkm_fifo_chan_init,
g84_fifo_chan_engine(struct nvkm_engine *engine)
{
switch (engine->subdev.index) {
- case NVDEV_ENGINE_GR : return 0;
- case NVDEV_ENGINE_MPEG :
- case NVDEV_ENGINE_MSPPP : return 1;
- case NVDEV_ENGINE_CE0 : return 2;
- case NVDEV_ENGINE_VP :
- case NVDEV_ENGINE_MSPDEC: return 3;
- case NVDEV_ENGINE_CIPHER:
- case NVDEV_ENGINE_SEC : return 4;
- case NVDEV_ENGINE_BSP :
- case NVDEV_ENGINE_MSVLD : return 5;
+ case NVKM_ENGINE_GR : return 0;
+ case NVKM_ENGINE_MPEG :
+ case NVKM_ENGINE_MSPPP : return 1;
+ case NVKM_ENGINE_CE0 : return 2;
+ case NVKM_ENGINE_VP :
+ case NVKM_ENGINE_MSPDEC: return 3;
+ case NVKM_ENGINE_CIPHER:
+ case NVKM_ENGINE_SEC : return 4;
+ case NVKM_ENGINE_BSP :
+ case NVKM_ENGINE_MSVLD : return 5;
default:
WARN_ON(1);
return 0;
g84_fifo_chan_engine_addr(struct nvkm_engine *engine)
{
switch (engine->subdev.index) {
- case NVDEV_ENGINE_DMAOBJ:
- case NVDEV_ENGINE_SW : return -1;
- case NVDEV_ENGINE_GR : return 0x0020;
- case NVDEV_ENGINE_VP :
- case NVDEV_ENGINE_MSPDEC: return 0x0040;
- case NVDEV_ENGINE_MPEG :
- case NVDEV_ENGINE_MSPPP : return 0x0060;
- case NVDEV_ENGINE_BSP :
- case NVDEV_ENGINE_MSVLD : return 0x0080;
- case NVDEV_ENGINE_CIPHER:
- case NVDEV_ENGINE_SEC : return 0x00a0;
- case NVDEV_ENGINE_CE0 : return 0x00c0;
+ case NVKM_ENGINE_DMAOBJ:
+ case NVKM_ENGINE_SW : return -1;
+ case NVKM_ENGINE_GR : return 0x0020;
+ case NVKM_ENGINE_VP :
+ case NVKM_ENGINE_MSPDEC: return 0x0040;
+ case NVKM_ENGINE_MPEG :
+ case NVKM_ENGINE_MSPPP : return 0x0060;
+ case NVKM_ENGINE_BSP :
+ case NVKM_ENGINE_MSVLD : return 0x0080;
+ case NVKM_ENGINE_CIPHER:
+ case NVKM_ENGINE_SEC : return 0x00a0;
+ case NVKM_ENGINE_CE0 : return 0x00c0;
default:
WARN_ON(1);
return -1;
if (g84_fifo_chan_engine_addr(engine) < 0)
return 0;
- if (nv_iclass(object, NV_GPUOBJ_CLASS)) {
- chan->engn[engn] = nv_gpuobj(object);
- return 0;
- }
-
return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]);
}
u32 context;
switch (object->engine->subdev.index) {
- case NVDEV_ENGINE_DMAOBJ:
- case NVDEV_ENGINE_SW : context = 0x00000000; break;
- case NVDEV_ENGINE_GR : context = 0x00100000; break;
- case NVDEV_ENGINE_MPEG :
- case NVDEV_ENGINE_MSPPP : context = 0x00200000; break;
- case NVDEV_ENGINE_ME :
- case NVDEV_ENGINE_CE0 : context = 0x00300000; break;
- case NVDEV_ENGINE_VP :
- case NVDEV_ENGINE_MSPDEC: context = 0x00400000; break;
- case NVDEV_ENGINE_CIPHER:
- case NVDEV_ENGINE_SEC :
- case NVDEV_ENGINE_VIC : context = 0x00500000; break;
- case NVDEV_ENGINE_BSP :
- case NVDEV_ENGINE_MSVLD : context = 0x00600000; break;
+ case NVKM_ENGINE_DMAOBJ:
+ case NVKM_ENGINE_SW : context = 0x00000000; break;
+ case NVKM_ENGINE_GR : context = 0x00100000; break;
+ case NVKM_ENGINE_MPEG :
+ case NVKM_ENGINE_MSPPP : context = 0x00200000; break;
+ case NVKM_ENGINE_ME :
+ case NVKM_ENGINE_CE0 : context = 0x00300000; break;
+ case NVKM_ENGINE_VP :
+ case NVKM_ENGINE_MSPDEC: context = 0x00400000; break;
+ case NVKM_ENGINE_CIPHER:
+ case NVKM_ENGINE_SEC :
+ case NVKM_ENGINE_VIC : context = 0x00500000; break;
+ case NVKM_ENGINE_BSP :
+ case NVKM_ENGINE_MSVLD : context = 0x00600000; break;
default:
WARN_ON(1);
return -EINVAL;
ret = nvkm_fifo_chan_ctor(&g84_fifo_chan_func, &fifo->base,
0x10000, 0x1000, false, vm, push,
- (1ULL << NVDEV_ENGINE_BSP) |
- (1ULL << NVDEV_ENGINE_CE0) |
- (1ULL << NVDEV_ENGINE_CIPHER) |
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_ME) |
- (1ULL << NVDEV_ENGINE_MPEG) |
- (1ULL << NVDEV_ENGINE_MSPDEC) |
- (1ULL << NVDEV_ENGINE_MSPPP) |
- (1ULL << NVDEV_ENGINE_MSVLD) |
- (1ULL << NVDEV_ENGINE_SEC) |
- (1ULL << NVDEV_ENGINE_SW) |
- (1ULL << NVDEV_ENGINE_VIC) |
- (1ULL << NVDEV_ENGINE_VP),
+ (1ULL << NVKM_ENGINE_BSP) |
+ (1ULL << NVKM_ENGINE_CE0) |
+ (1ULL << NVKM_ENGINE_CIPHER) |
+ (1ULL << NVKM_ENGINE_DMAOBJ) |
+ (1ULL << NVKM_ENGINE_GR) |
+ (1ULL << NVKM_ENGINE_ME) |
+ (1ULL << NVKM_ENGINE_MPEG) |
+ (1ULL << NVKM_ENGINE_MSPDEC) |
+ (1ULL << NVKM_ENGINE_MSPPP) |
+ (1ULL << NVKM_ENGINE_MSVLD) |
+ (1ULL << NVKM_ENGINE_SEC) |
+ (1ULL << NVKM_ENGINE_SW) |
+ (1ULL << NVKM_ENGINE_VIC) |
+ (1ULL << NVKM_ENGINE_VP),
0, 0xc00000, 0x2000, oclass, &chan->base);
chan->fifo = fifo;
if (ret)
struct {
struct nvkm_gpuobj *inst;
struct nvkm_vma vma;
- } engn[NVDEV_SUBDEV_NR];
+ } engn[NVKM_SUBDEV_NR];
};
extern const struct nvkm_fifo_chan_oclass gf100_fifo_gpfifo_oclass;
struct {
struct nvkm_gpuobj *inst;
struct nvkm_vma vma;
- } engn[NVDEV_SUBDEV_NR];
+ } engn[NVKM_SUBDEV_NR];
};
int gk104_fifo_gpfifo_new(struct nvkm_fifo *, const struct nvkm_oclass *,
struct nvkm_fifo_chan base;
struct nv04_fifo *fifo;
u32 ramfc;
- struct nvkm_gpuobj *engn[NVDEV_SUBDEV_NR];
+ struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR];
};
extern const struct nvkm_fifo_chan_func nv04_fifo_dma_func;
nv50_fifo_chan_engine_addr(struct nvkm_engine *engine)
{
switch (engine->subdev.index) {
- case NVDEV_ENGINE_DMAOBJ:
- case NVDEV_ENGINE_SW : return -1;
- case NVDEV_ENGINE_GR : return 0x0000;
- case NVDEV_ENGINE_MPEG : return 0x0060;
+ case NVKM_ENGINE_DMAOBJ:
+ case NVKM_ENGINE_SW : return -1;
+ case NVKM_ENGINE_GR : return 0x0000;
+ case NVKM_ENGINE_MPEG : return 0x0060;
default:
WARN_ON(1);
return -1;
struct nvkm_engine *engine)
{
struct nv50_fifo_chan *chan = nv50_fifo_chan(base);
- if (!chan->engn[engine->subdev.index] ||
- chan->engn[engine->subdev.index]->object.oclass) {
- chan->engn[engine->subdev.index] = NULL;
- return;
- }
nvkm_gpuobj_del(&chan->engn[engine->subdev.index]);
}
if (nv50_fifo_chan_engine_addr(engine) < 0)
return 0;
- if (nv_iclass(object, NV_GPUOBJ_CLASS)) {
- chan->engn[engn] = nv_gpuobj(object);
- return 0;
- }
-
return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]);
}
u32 context;
switch (object->engine->subdev.index) {
- case NVDEV_ENGINE_DMAOBJ:
- case NVDEV_ENGINE_SW : context = 0x00000000; break;
- case NVDEV_ENGINE_GR : context = 0x00100000; break;
- case NVDEV_ENGINE_MPEG : context = 0x00200000; break;
+ case NVKM_ENGINE_DMAOBJ:
+ case NVKM_ENGINE_SW : context = 0x00000000; break;
+ case NVKM_ENGINE_GR : context = 0x00100000; break;
+ case NVKM_ENGINE_MPEG : context = 0x00200000; break;
default:
WARN_ON(1);
return -EINVAL;
ret = nvkm_fifo_chan_ctor(&nv50_fifo_chan_func, &fifo->base,
0x10000, 0x1000, false, vm, push,
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_SW) |
- (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_MPEG),
+ (1ULL << NVKM_ENGINE_DMAOBJ) |
+ (1ULL << NVKM_ENGINE_SW) |
+ (1ULL << NVKM_ENGINE_GR) |
+ (1ULL << NVKM_ENGINE_MPEG),
0, 0xc00000, 0x2000, oclass, &chan->base);
chan->fifo = fifo;
if (ret)
struct nvkm_ramht *ramht;
struct nvkm_vm *vm;
- struct nvkm_gpuobj *engn[NVDEV_SUBDEV_NR];
+ struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR];
};
int nv50_fifo_chan_ctor(struct nv50_fifo *, u64 vm, u64 push,
int hash;
switch (object->engine->subdev.index) {
- case NVDEV_ENGINE_DMAOBJ:
- case NVDEV_ENGINE_SW : context |= 0x00000000; break;
- case NVDEV_ENGINE_GR : context |= 0x00010000; break;
- case NVDEV_ENGINE_MPEG : context |= 0x00020000; break;
+ case NVKM_ENGINE_DMAOBJ:
+ case NVKM_ENGINE_SW : context |= 0x00000000; break;
+ case NVKM_ENGINE_GR : context |= 0x00010000; break;
+ case NVKM_ENGINE_MPEG : context |= 0x00020000; break;
default:
WARN_ON(1);
return -EINVAL;
ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base,
0x1000, 0x1000, false, 0, args->v0.pushbuf,
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_SW),
+ (1ULL << NVKM_ENGINE_DMAOBJ) |
+ (1ULL << NVKM_ENGINE_GR) |
+ (1ULL << NVKM_ENGINE_SW),
0, 0x800000, 0x10000, oclass, &chan->base);
chan->fifo = fifo;
if (ret)
ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base,
0x1000, 0x1000, false, 0, args->v0.pushbuf,
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_SW),
+ (1ULL << NVKM_ENGINE_DMAOBJ) |
+ (1ULL << NVKM_ENGINE_GR) |
+ (1ULL << NVKM_ENGINE_SW),
0, 0x800000, 0x10000, oclass, &chan->base);
chan->fifo = fifo;
if (ret)
ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base,
0x1000, 0x1000, false, 0, args->v0.pushbuf,
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_MPEG) | /* NV31- */
- (1ULL << NVDEV_ENGINE_SW),
+ (1ULL << NVKM_ENGINE_DMAOBJ) |
+ (1ULL << NVKM_ENGINE_GR) |
+ (1ULL << NVKM_ENGINE_MPEG) | /* NV31- */
+ (1ULL << NVKM_ENGINE_SW),
0, 0x800000, 0x10000, oclass, &chan->base);
chan->fifo = fifo;
if (ret)
nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx)
{
switch (engine->subdev.index) {
- case NVDEV_ENGINE_DMAOBJ:
- case NVDEV_ENGINE_SW:
+ case NVKM_ENGINE_DMAOBJ:
+ case NVKM_ENGINE_SW:
return false;
- case NVDEV_ENGINE_GR:
+ case NVKM_ENGINE_GR:
*reg = 0x0032e0;
*ctx = 0x38;
return true;
- case NVDEV_ENGINE_MPEG:
+ case NVKM_ENGINE_MPEG:
*reg = 0x00330c;
*ctx = 0x54;
return true;
struct nvkm_engine *engine)
{
struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
- if (!chan->engn[engine->subdev.index] ||
- chan->engn[engine->subdev.index]->object.oclass) {
- chan->engn[engine->subdev.index] = NULL;
- return;
- }
nvkm_gpuobj_del(&chan->engn[engine->subdev.index]);
}
if (!nv40_fifo_dma_engine(engine, ®, &ctx))
return 0;
- if (nv_iclass(object, NV_GPUOBJ_CLASS)) {
- chan->engn[engn] = nv_gpuobj(object);
- return 0;
- }
-
return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]);
}
int hash;
switch (object->engine->subdev.index) {
- case NVDEV_ENGINE_DMAOBJ:
- case NVDEV_ENGINE_SW : context |= 0x00000000; break;
- case NVDEV_ENGINE_GR : context |= 0x00100000; break;
- case NVDEV_ENGINE_MPEG : context |= 0x00200000; break;
+ case NVKM_ENGINE_DMAOBJ:
+ case NVKM_ENGINE_SW : context |= 0x00000000; break;
+ case NVKM_ENGINE_GR : context |= 0x00100000; break;
+ case NVKM_ENGINE_MPEG : context |= 0x00200000; break;
default:
WARN_ON(1);
return -EINVAL;
ret = nvkm_fifo_chan_ctor(&nv40_fifo_dma_func, &fifo->base,
0x1000, 0x1000, false, 0, args->v0.pushbuf,
- (1ULL << NVDEV_ENGINE_DMAOBJ) |
- (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_MPEG) |
- (1ULL << NVDEV_ENGINE_SW),
+ (1ULL << NVKM_ENGINE_DMAOBJ) |
+ (1ULL << NVKM_ENGINE_GR) |
+ (1ULL << NVKM_ENGINE_MPEG) |
+ (1ULL << NVKM_ENGINE_SW),
0, 0xc00000, 0x1000, oclass, &chan->base);
chan->fifo = fifo;
if (ret)
gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn)
{
switch (engn) {
- case NVDEV_ENGINE_GR : engn = 0; break;
- case NVDEV_ENGINE_MSVLD : engn = 1; break;
- case NVDEV_ENGINE_MSPPP : engn = 2; break;
- case NVDEV_ENGINE_MSPDEC: engn = 3; break;
- case NVDEV_ENGINE_CE0 : engn = 4; break;
- case NVDEV_ENGINE_CE1 : engn = 5; break;
+ case NVKM_ENGINE_GR : engn = 0; break;
+ case NVKM_ENGINE_MSVLD : engn = 1; break;
+ case NVKM_ENGINE_MSPPP : engn = 2; break;
+ case NVKM_ENGINE_MSPDEC: engn = 3; break;
+ case NVKM_ENGINE_CE0 : engn = 4; break;
+ case NVKM_ENGINE_CE1 : engn = 5; break;
default:
return -1;
}
struct nvkm_device *device = fifo->base.engine.subdev.device;
switch (engn) {
- case 0: engn = NVDEV_ENGINE_GR; break;
- case 1: engn = NVDEV_ENGINE_MSVLD; break;
- case 2: engn = NVDEV_ENGINE_MSPPP; break;
- case 3: engn = NVDEV_ENGINE_MSPDEC; break;
- case 4: engn = NVDEV_ENGINE_CE0; break;
- case 5: engn = NVDEV_ENGINE_CE1; break;
+ case 0: engn = NVKM_ENGINE_GR; break;
+ case 1: engn = NVKM_ENGINE_MSVLD; break;
+ case 2: engn = NVKM_ENGINE_MSPPP; break;
+ case 3: engn = NVKM_ENGINE_MSPDEC; break;
+ case 4: engn = NVKM_ENGINE_CE0; break;
+ case 5: engn = NVKM_ENGINE_CE1; break;
default:
return NULL;
}
static const struct nvkm_enum
gf100_fifo_fault_engine[] = {
- { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
- { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB },
- { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
- { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
- { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
- { 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD },
- { 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
+ { 0x00, "PGRAPH", NULL, NVKM_ENGINE_GR },
+ { 0x03, "PEEPHOLE", NULL, NVKM_ENGINE_IFB },
+ { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
+ { 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM },
+ { 0x07, "PFIFO", NULL, NVKM_ENGINE_FIFO },
+ { 0x10, "PMSVLD", NULL, NVKM_ENGINE_MSVLD },
+ { 0x11, "PMSPPP", NULL, NVKM_ENGINE_MSPPP },
{ 0x13, "PCOUNTER" },
- { 0x14, "PMSPDEC", NULL, NVDEV_ENGINE_MSPDEC },
- { 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 },
- { 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 },
+ { 0x14, "PMSPDEC", NULL, NVKM_ENGINE_MSPDEC },
+ { 0x15, "PCE0", NULL, NVKM_ENGINE_CE0 },
+ { 0x16, "PCE1", NULL, NVKM_ENGINE_CE1 },
{ 0x17, "PDAEMON" },
{}
};
if (eu) {
switch (eu->data2) {
- case NVDEV_SUBDEV_BAR:
+ case NVKM_SUBDEV_BAR:
nvkm_mask(device, 0x001704, 0x00000000, 0x00000000);
break;
- case NVDEV_SUBDEV_INSTMEM:
+ case NVKM_SUBDEV_INSTMEM:
nvkm_mask(device, 0x001714, 0x00000000, 0x00000000);
break;
- case NVDEV_ENGINE_IFB:
+ case NVKM_ENGINE_IFB:
nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
break;
default:
static const struct nvkm_enum
gk104_fifo_fault_engine[] = {
- { 0x00, "GR", NULL, NVDEV_ENGINE_GR },
- { 0x03, "IFB", NULL, NVDEV_ENGINE_IFB },
- { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
- { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
- { 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO },
- { 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO },
- { 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO },
- { 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD },
- { 0x11, "MSPPP", NULL, NVDEV_ENGINE_MSPPP },
+ { 0x00, "GR", NULL, NVKM_ENGINE_GR },
+ { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
+ { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
+ { 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM },
+ { 0x07, "PBDMA0", NULL, NVKM_ENGINE_FIFO },
+ { 0x08, "PBDMA1", NULL, NVKM_ENGINE_FIFO },
+ { 0x09, "PBDMA2", NULL, NVKM_ENGINE_FIFO },
+ { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD },
+ { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP },
{ 0x13, "PERF" },
- { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_MSPDEC },
- { 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 },
- { 0x16, "CE1", NULL, NVDEV_ENGINE_CE1 },
+ { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC },
+ { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 },
+ { 0x16, "CE1", NULL, NVKM_ENGINE_CE1 },
{ 0x17, "PMU" },
- { 0x19, "MSENC", NULL, NVDEV_ENGINE_MSENC },
- { 0x1b, "CE2", NULL, NVDEV_ENGINE_CE2 },
+ { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC },
+ { 0x1b, "CE2", NULL, NVKM_ENGINE_CE2 },
{}
};
if (eu) {
switch (eu->data2) {
- case NVDEV_SUBDEV_BAR:
+ case NVKM_SUBDEV_BAR:
nvkm_mask(device, 0x001704, 0x00000000, 0x00000000);
break;
- case NVDEV_SUBDEV_INSTMEM:
+ case NVKM_SUBDEV_INSTMEM:
nvkm_mask(device, 0x001714, 0x00000000, 0x00000000);
break;
- case NVDEV_ENGINE_IFB:
+ case NVKM_ENGINE_IFB:
nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
break;
default:
gk104_fifo_engine_subdev(int engine)
{
switch (engine) {
- case 0: return (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_SW) |
- (1ULL << NVDEV_ENGINE_CE2);
- case 1: return (1ULL << NVDEV_ENGINE_MSPDEC);
- case 2: return (1ULL << NVDEV_ENGINE_MSPPP);
- case 3: return (1ULL << NVDEV_ENGINE_MSVLD);
- case 4: return (1ULL << NVDEV_ENGINE_CE0);
- case 5: return (1ULL << NVDEV_ENGINE_CE1);
- case 6: return (1ULL << NVDEV_ENGINE_MSENC);
+ case 0: return (1ULL << NVKM_ENGINE_GR) |
+ (1ULL << NVKM_ENGINE_SW) |
+ (1ULL << NVKM_ENGINE_CE2);
+ case 1: return (1ULL << NVKM_ENGINE_MSPDEC);
+ case 2: return (1ULL << NVKM_ENGINE_MSPPP);
+ case 3: return (1ULL << NVKM_ENGINE_MSVLD);
+ case 4: return (1ULL << NVKM_ENGINE_CE0);
+ case 5: return (1ULL << NVKM_ENGINE_CE1);
+ case 6: return (1ULL << NVKM_ENGINE_MSENC);
default:
WARN_ON(1);
return 0;
gk104_fifo_subdev_engine(int subdev)
{
switch (subdev) {
- case NVDEV_ENGINE_GR:
- case NVDEV_ENGINE_SW:
- case NVDEV_ENGINE_CE2 : return 0;
- case NVDEV_ENGINE_MSPDEC: return 1;
- case NVDEV_ENGINE_MSPPP : return 2;
- case NVDEV_ENGINE_MSVLD : return 3;
- case NVDEV_ENGINE_CE0 : return 4;
- case NVDEV_ENGINE_CE1 : return 5;
- case NVDEV_ENGINE_MSENC : return 6;
+ case NVKM_ENGINE_GR:
+ case NVKM_ENGINE_SW:
+ case NVKM_ENGINE_CE2 : return 0;
+ case NVKM_ENGINE_MSPDEC: return 1;
+ case NVKM_ENGINE_MSPPP : return 2;
+ case NVKM_ENGINE_MSVLD : return 3;
+ case NVKM_ENGINE_CE0 : return 4;
+ case NVKM_ENGINE_CE1 : return 5;
+ case NVKM_ENGINE_MSENC : return 6;
default:
WARN_ON(1);
return 0;
gf100_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
{
switch (engine->subdev.index) {
- case NVDEV_ENGINE_SW : return 0;
- case NVDEV_ENGINE_GR : return 0x0210;
- case NVDEV_ENGINE_CE0 : return 0x0230;
- case NVDEV_ENGINE_CE1 : return 0x0240;
- case NVDEV_ENGINE_MSPDEC: return 0x0250;
- case NVDEV_ENGINE_MSPPP : return 0x0260;
- case NVDEV_ENGINE_MSVLD : return 0x0270;
+ case NVKM_ENGINE_SW : return 0;
+ case NVKM_ENGINE_GR : return 0x0210;
+ case NVKM_ENGINE_CE0 : return 0x0230;
+ case NVKM_ENGINE_CE1 : return 0x0240;
+ case NVKM_ENGINE_MSPDEC: return 0x0250;
+ case NVKM_ENGINE_MSPPP : return 0x0260;
+ case NVKM_ENGINE_MSVLD : return 0x0270;
default:
WARN_ON(1);
return 0;
if (!gf100_fifo_gpfifo_engine_addr(engine))
return 0;
- if (object->oclass) {
- return nvkm_gpuobj_map(nv_gpuobj(object), chan->vm,
- NV_MEM_ACCESS_RW,
- &chan->engn[engn].vma);
- }
-
ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst);
if (ret)
return ret;
ret = nvkm_fifo_chan_ctor(&gf100_fifo_gpfifo_func, &fifo->base,
0x1000, 0x1000, true, args->v0.vm, 0,
- (1ULL << NVDEV_ENGINE_CE0) |
- (1ULL << NVDEV_ENGINE_CE1) |
- (1ULL << NVDEV_ENGINE_GR) |
- (1ULL << NVDEV_ENGINE_MSPDEC) |
- (1ULL << NVDEV_ENGINE_MSPPP) |
- (1ULL << NVDEV_ENGINE_MSVLD) |
- (1ULL << NVDEV_ENGINE_SW),
+ (1ULL << NVKM_ENGINE_CE0) |
+ (1ULL << NVKM_ENGINE_CE1) |
+ (1ULL << NVKM_ENGINE_GR) |
+ (1ULL << NVKM_ENGINE_MSPDEC) |
+ (1ULL << NVKM_ENGINE_MSPPP) |
+ (1ULL << NVKM_ENGINE_MSVLD) |
+ (1ULL << NVKM_ENGINE_SW),
1, fifo->user.bar.offset, 0x1000,
oclass, &chan->base);
if (ret)
gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
{
switch (engine->subdev.index) {
- case NVDEV_ENGINE_SW :
- case NVDEV_ENGINE_CE0 :
- case NVDEV_ENGINE_CE1 :
- case NVDEV_ENGINE_CE2 : return 0x0000;
- case NVDEV_ENGINE_GR : return 0x0210;
- case NVDEV_ENGINE_MSPDEC: return 0x0250;
- case NVDEV_ENGINE_MSPPP : return 0x0260;
- case NVDEV_ENGINE_MSVLD : return 0x0270;
+ case NVKM_ENGINE_SW :
+ case NVKM_ENGINE_CE0 :
+ case NVKM_ENGINE_CE1 :
+ case NVKM_ENGINE_CE2 : return 0x0000;
+ case NVKM_ENGINE_GR : return 0x0210;
+ case NVKM_ENGINE_MSPDEC: return 0x0250;
+ case NVKM_ENGINE_MSPPP : return 0x0260;
+ case NVKM_ENGINE_MSVLD : return 0x0270;
default:
WARN_ON(1);
return 0;
if (!gk104_fifo_gpfifo_engine_addr(engine))
return 0;
- if (object->oclass) {
- return nvkm_gpuobj_map(nv_gpuobj(object), chan->vm,
- NV_MEM_ACCESS_RW,
- &chan->engn[engn].vma);
- }
-
ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst);
if (ret)
return ret;
false, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
- nvkm_wo32(*pgpuobj, 0x00, object->oclass_name);
+ nvkm_wo32(*pgpuobj, 0x00, object->oclass);
nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
#ifdef __BIG_ENDIAN
false, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
- nvkm_wo32(*pgpuobj, 0x00, object->oclass_name);
+ nvkm_wo32(*pgpuobj, 0x00, object->oclass);
nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
#ifdef __BIG_ENDIAN
align, false, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
- nvkm_wo32(*pgpuobj, 0x00, object->oclass_name);
+ nvkm_wo32(*pgpuobj, 0x00, object->oclass);
nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
false, parent, pgpuobj);
if (ret == 0) {
nvkm_kmap(*pgpuobj);
- nvkm_wo32(*pgpuobj, 0x00, object->oclass_name);
+ nvkm_wo32(*pgpuobj, 0x00, object->oclass);
nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
if (ret)
return ret;
- atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
+ atomic_inc(&vm->engref[NVKM_SUBDEV_BAR]);
/*
* Bootstrap page table lookup.
if (ret)
return ret;
- atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
+ atomic_inc(&vm->engref[NVKM_SUBDEV_BAR]);
ret = nvkm_vm_boot(vm, limit-- - start);
if (ret)
if (ret)
return ret;
- atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
+ atomic_inc(&vm->engref[NVKM_SUBDEV_BAR]);
ret = nvkm_vm_ref(vm, &bar->bar1_vm, bar->pgd);
nvkm_vm_ref(NULL, &vm, NULL);
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
- disable |= (1ULL << NVDEV_ENGINE_MPEG);
- disable |= (1ULL << NVDEV_ENGINE_VP);
- disable |= (1ULL << NVDEV_ENGINE_BSP);
- disable |= (1ULL << NVDEV_ENGINE_CIPHER);
+ disable |= (1ULL << NVKM_ENGINE_MPEG);
+ disable |= (1ULL << NVKM_ENGINE_VP);
+ disable |= (1ULL << NVKM_ENGINE_BSP);
+ disable |= (1ULL << NVKM_ENGINE_CIPHER);
}
if (!(r00154c & 0x00000004))
- disable |= (1ULL << NVDEV_ENGINE_DISP);
+ disable |= (1ULL << NVKM_ENGINE_DISP);
if (!(r00154c & 0x00000020))
- disable |= (1ULL << NVDEV_ENGINE_BSP);
+ disable |= (1ULL << NVKM_ENGINE_BSP);
if (!(r00154c & 0x00000040))
- disable |= (1ULL << NVDEV_ENGINE_CIPHER);
+ disable |= (1ULL << NVKM_ENGINE_CIPHER);
return disable;
}
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
- disable |= (1ULL << NVDEV_ENGINE_MSPDEC);
- disable |= (1ULL << NVDEV_ENGINE_MSVLD);
- disable |= (1ULL << NVDEV_ENGINE_MSPPP);
+ disable |= (1ULL << NVKM_ENGINE_MSPDEC);
+ disable |= (1ULL << NVKM_ENGINE_MSVLD);
+ disable |= (1ULL << NVKM_ENGINE_MSPPP);
}
if (!(r00154c & 0x00000004))
- disable |= (1ULL << NVDEV_ENGINE_DISP);
+ disable |= (1ULL << NVKM_ENGINE_DISP);
if (!(r00154c & 0x00000020))
- disable |= (1ULL << NVDEV_ENGINE_MSVLD);
+ disable |= (1ULL << NVKM_ENGINE_MSVLD);
if (!(r00154c & 0x00000040))
- disable |= (1ULL << NVDEV_ENGINE_SEC);
+ disable |= (1ULL << NVKM_ENGINE_SEC);
return disable;
}
u64 disable = 0ULL;
if (r022500 & 0x00000001)
- disable |= (1ULL << NVDEV_ENGINE_DISP);
+ disable |= (1ULL << NVKM_ENGINE_DISP);
if (r022500 & 0x00000002) {
- disable |= (1ULL << NVDEV_ENGINE_MSPDEC);
- disable |= (1ULL << NVDEV_ENGINE_MSPPP);
+ disable |= (1ULL << NVKM_ENGINE_MSPDEC);
+ disable |= (1ULL << NVKM_ENGINE_MSPPP);
}
if (r022500 & 0x00000004)
- disable |= (1ULL << NVDEV_ENGINE_MSVLD);
+ disable |= (1ULL << NVKM_ENGINE_MSVLD);
if (r022500 & 0x00000008)
- disable |= (1ULL << NVDEV_ENGINE_MSENC);
+ disable |= (1ULL << NVKM_ENGINE_MSENC);
if (r022500 & 0x00000100)
- disable |= (1ULL << NVDEV_ENGINE_CE0);
+ disable |= (1ULL << NVKM_ENGINE_CE0);
if (r022500 & 0x00000200)
- disable |= (1ULL << NVDEV_ENGINE_CE1);
+ disable |= (1ULL << NVKM_ENGINE_CE1);
return disable;
}
u64 disable = 0ULL;
if (r021c00 & 0x00000001)
- disable |= (1ULL << NVDEV_ENGINE_CE0);
+ disable |= (1ULL << NVKM_ENGINE_CE0);
if (r021c00 & 0x00000004)
- disable |= (1ULL << NVDEV_ENGINE_CE2);
+ disable |= (1ULL << NVKM_ENGINE_CE2);
if (r021c04 & 0x00000001)
- disable |= (1ULL << NVDEV_ENGINE_DISP);
+ disable |= (1ULL << NVKM_ENGINE_DISP);
return disable;
}
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
- disable |= (1ULL << NVDEV_ENGINE_MSPDEC);
- disable |= (1ULL << NVDEV_ENGINE_MSPPP);
+ disable |= (1ULL << NVKM_ENGINE_MSPDEC);
+ disable |= (1ULL << NVKM_ENGINE_MSPPP);
}
if (!(r00154c & 0x00000004))
- disable |= (1ULL << NVDEV_ENGINE_DISP);
+ disable |= (1ULL << NVKM_ENGINE_DISP);
if (!(r00154c & 0x00000020))
- disable |= (1ULL << NVDEV_ENGINE_MSVLD);
+ disable |= (1ULL << NVKM_ENGINE_MSVLD);
if (!(r00154c & 0x00000200))
- disable |= (1ULL << NVDEV_ENGINE_CE0);
+ disable |= (1ULL << NVKM_ENGINE_CE0);
return disable;
}
u64 disable = 0;
if (!(r001540 & 0x40000000)) {
- disable |= (1ULL << NVDEV_ENGINE_MSPDEC);
- disable |= (1ULL << NVDEV_ENGINE_MSPPP);
+ disable |= (1ULL << NVKM_ENGINE_MSPDEC);
+ disable |= (1ULL << NVKM_ENGINE_MSPPP);
}
if (!(r00154c & 0x00000004))
- disable |= (1ULL << NVDEV_ENGINE_DISP);
+ disable |= (1ULL << NVKM_ENGINE_DISP);
if (!(r00154c & 0x00000020))
- disable |= (1ULL << NVDEV_ENGINE_MSVLD);
+ disable |= (1ULL << NVKM_ENGINE_MSVLD);
if (!(r00154c & 0x00000040))
- disable |= (1ULL << NVDEV_ENGINE_VIC);
+ disable |= (1ULL << NVKM_ENGINE_VIC);
if (!(r00154c & 0x00000200))
- disable |= (1ULL << NVDEV_ENGINE_CE0);
+ disable |= (1ULL << NVKM_ENGINE_CE0);
return disable;
}
u64 disable = 0ULL;
if (!(r001540 & 0x40000000))
- disable |= (1ULL << NVDEV_ENGINE_MPEG);
+ disable |= (1ULL << NVKM_ENGINE_MPEG);
return disable;
}
*/
if (!init->base.post) {
u64 disable = nvkm_devinit_disable(&init->base);
- if (disable & (1ULL << NVDEV_ENGINE_DISP))
+ if (disable & (1ULL << NVKM_ENGINE_DISP))
init->base.post = true;
}
static const struct nvkm_mc_intr
g98_mc_intr[] = {
- { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */
- { 0x00000001, NVDEV_ENGINE_MSPPP },
- { 0x00000100, NVDEV_ENGINE_FIFO },
- { 0x00001000, NVDEV_ENGINE_GR },
- { 0x00004000, NVDEV_ENGINE_SEC }, /* NV84:NVA3 */
- { 0x00008000, NVDEV_ENGINE_MSVLD },
- { 0x00020000, NVDEV_ENGINE_MSPDEC },
- { 0x00040000, NVDEV_SUBDEV_PMU }, /* NVA3:NVC0 */
- { 0x00080000, NVDEV_SUBDEV_THERM }, /* NVA3:NVC0 */
- { 0x00100000, NVDEV_SUBDEV_TIMER },
- { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */
- { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */
- { 0x00400000, NVDEV_ENGINE_CE0 }, /* NVA3- */
- { 0x10000000, NVDEV_SUBDEV_BUS },
- { 0x80000000, NVDEV_ENGINE_SW },
- { 0x0042d101, NVDEV_SUBDEV_FB },
+ { 0x04000000, NVKM_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */
+ { 0x00000001, NVKM_ENGINE_MSPPP },
+ { 0x00000100, NVKM_ENGINE_FIFO },
+ { 0x00001000, NVKM_ENGINE_GR },
+ { 0x00004000, NVKM_ENGINE_SEC }, /* NV84:NVA3 */
+ { 0x00008000, NVKM_ENGINE_MSVLD },
+ { 0x00020000, NVKM_ENGINE_MSPDEC },
+ { 0x00040000, NVKM_SUBDEV_PMU }, /* NVA3:NVC0 */
+ { 0x00080000, NVKM_SUBDEV_THERM }, /* NVA3:NVC0 */
+ { 0x00100000, NVKM_SUBDEV_TIMER },
+ { 0x00200000, NVKM_SUBDEV_GPIO }, /* PMGR->GPIO */
+ { 0x00200000, NVKM_SUBDEV_I2C }, /* PMGR->I2C/AUX */
+ { 0x00400000, NVKM_ENGINE_CE0 }, /* NVA3- */
+ { 0x10000000, NVKM_SUBDEV_BUS },
+ { 0x80000000, NVKM_ENGINE_SW },
+ { 0x0042d101, NVKM_SUBDEV_FB },
{},
};
const struct nvkm_mc_intr
gf100_mc_intr[] = {
- { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */
- { 0x00000001, NVDEV_ENGINE_MSPPP },
- { 0x00000020, NVDEV_ENGINE_CE0 },
- { 0x00000040, NVDEV_ENGINE_CE1 },
- { 0x00000080, NVDEV_ENGINE_CE2 },
- { 0x00000100, NVDEV_ENGINE_FIFO },
- { 0x00001000, NVDEV_ENGINE_GR },
- { 0x00002000, NVDEV_SUBDEV_FB },
- { 0x00008000, NVDEV_ENGINE_MSVLD },
- { 0x00040000, NVDEV_SUBDEV_THERM },
- { 0x00020000, NVDEV_ENGINE_MSPDEC },
- { 0x00100000, NVDEV_SUBDEV_TIMER },
- { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */
- { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */
- { 0x01000000, NVDEV_SUBDEV_PMU },
- { 0x02000000, NVDEV_SUBDEV_LTC },
- { 0x08000000, NVDEV_SUBDEV_FB },
- { 0x10000000, NVDEV_SUBDEV_BUS },
- { 0x40000000, NVDEV_SUBDEV_IBUS },
- { 0x80000000, NVDEV_ENGINE_SW },
+ { 0x04000000, NVKM_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */
+ { 0x00000001, NVKM_ENGINE_MSPPP },
+ { 0x00000020, NVKM_ENGINE_CE0 },
+ { 0x00000040, NVKM_ENGINE_CE1 },
+ { 0x00000080, NVKM_ENGINE_CE2 },
+ { 0x00000100, NVKM_ENGINE_FIFO },
+ { 0x00001000, NVKM_ENGINE_GR },
+ { 0x00002000, NVKM_SUBDEV_FB },
+ { 0x00008000, NVKM_ENGINE_MSVLD },
+ { 0x00040000, NVKM_SUBDEV_THERM },
+ { 0x00020000, NVKM_ENGINE_MSPDEC },
+ { 0x00100000, NVKM_SUBDEV_TIMER },
+ { 0x00200000, NVKM_SUBDEV_GPIO }, /* PMGR->GPIO */
+ { 0x00200000, NVKM_SUBDEV_I2C }, /* PMGR->I2C/AUX */
+ { 0x01000000, NVKM_SUBDEV_PMU },
+ { 0x02000000, NVKM_SUBDEV_LTC },
+ { 0x08000000, NVKM_SUBDEV_FB },
+ { 0x10000000, NVKM_SUBDEV_BUS },
+ { 0x40000000, NVKM_SUBDEV_IBUS },
+ { 0x80000000, NVKM_ENGINE_SW },
{},
};
const struct nvkm_mc_intr
nv04_mc_intr[] = {
- { 0x00000001, NVDEV_ENGINE_MPEG }, /* NV17- MPEG/ME */
- { 0x00000100, NVDEV_ENGINE_FIFO },
- { 0x00001000, NVDEV_ENGINE_GR },
- { 0x00010000, NVDEV_ENGINE_DISP },
- { 0x00020000, NVDEV_ENGINE_VP }, /* NV40- */
- { 0x00100000, NVDEV_SUBDEV_TIMER },
- { 0x01000000, NVDEV_ENGINE_DISP }, /* NV04- PCRTC0 */
- { 0x02000000, NVDEV_ENGINE_DISP }, /* NV11- PCRTC1 */
- { 0x10000000, NVDEV_SUBDEV_BUS },
- { 0x80000000, NVDEV_ENGINE_SW },
+ { 0x00000001, NVKM_ENGINE_MPEG }, /* NV17- MPEG/ME */
+ { 0x00000100, NVKM_ENGINE_FIFO },
+ { 0x00001000, NVKM_ENGINE_GR },
+ { 0x00010000, NVKM_ENGINE_DISP },
+ { 0x00020000, NVKM_ENGINE_VP }, /* NV40- */
+ { 0x00100000, NVKM_SUBDEV_TIMER },
+ { 0x01000000, NVKM_ENGINE_DISP }, /* NV04- PCRTC0 */
+ { 0x02000000, NVKM_ENGINE_DISP }, /* NV11- PCRTC1 */
+ { 0x10000000, NVKM_SUBDEV_BUS },
+ { 0x80000000, NVKM_ENGINE_SW },
{}
};
const struct nvkm_mc_intr
nv50_mc_intr[] = {
- { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */
- { 0x00000001, NVDEV_ENGINE_MPEG },
- { 0x00000100, NVDEV_ENGINE_FIFO },
- { 0x00001000, NVDEV_ENGINE_GR },
- { 0x00004000, NVDEV_ENGINE_CIPHER }, /* NV84- */
- { 0x00008000, NVDEV_ENGINE_BSP }, /* NV84- */
- { 0x00020000, NVDEV_ENGINE_VP }, /* NV84- */
- { 0x00100000, NVDEV_SUBDEV_TIMER },
- { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */
- { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */
- { 0x10000000, NVDEV_SUBDEV_BUS },
- { 0x80000000, NVDEV_ENGINE_SW },
- { 0x0002d101, NVDEV_SUBDEV_FB },
+ { 0x04000000, NVKM_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */
+ { 0x00000001, NVKM_ENGINE_MPEG },
+ { 0x00000100, NVKM_ENGINE_FIFO },
+ { 0x00001000, NVKM_ENGINE_GR },
+ { 0x00004000, NVKM_ENGINE_CIPHER }, /* NV84- */
+ { 0x00008000, NVKM_ENGINE_BSP }, /* NV84- */
+ { 0x00020000, NVKM_ENGINE_VP }, /* NV84- */
+ { 0x00100000, NVKM_SUBDEV_TIMER },
+ { 0x00200000, NVKM_SUBDEV_GPIO }, /* PMGR->GPIO */
+ { 0x00200000, NVKM_SUBDEV_I2C }, /* PMGR->I2C/AUX */
+ { 0x10000000, NVKM_SUBDEV_BUS },
+ { 0x80000000, NVKM_ENGINE_SW },
+ { 0x0002d101, NVKM_SUBDEV_FB },
{},
};
u32 type;
type = 0x00000001; /* PAGE_ALL */
- if (atomic_read(&vm->engref[NVDEV_SUBDEV_BAR]))
+ if (atomic_read(&vm->engref[NVKM_SUBDEV_BAR]))
type |= 0x00000004; /* HUB_ONLY */
mutex_lock(&mmu->subdev.mutex);
int i, vme;
mutex_lock(&subdev->mutex);
- for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
+ for (i = 0; i < NVKM_SUBDEV_NR; i++) {
if (!atomic_read(&vm->engref[i]))
continue;
/* unfortunate hw bug workaround... */
- if (i == NVDEV_ENGINE_GR && device->gr) {
+ if (i == NVKM_ENGINE_GR && device->gr) {
int ret = nvkm_gr_tlb_flush(device->gr);
if (ret != -ENODEV)
continue;
}
switch (i) {
- case NVDEV_ENGINE_GR : vme = 0x00; break;
- case NVDEV_ENGINE_VP :
- case NVDEV_ENGINE_MSPDEC: vme = 0x01; break;
- case NVDEV_SUBDEV_BAR : vme = 0x06; break;
- case NVDEV_ENGINE_MSPPP :
- case NVDEV_ENGINE_MPEG : vme = 0x08; break;
- case NVDEV_ENGINE_BSP :
- case NVDEV_ENGINE_MSVLD : vme = 0x09; break;
- case NVDEV_ENGINE_CIPHER:
- case NVDEV_ENGINE_SEC : vme = 0x0a; break;
- case NVDEV_ENGINE_CE0 : vme = 0x0d; break;
+ case NVKM_ENGINE_GR : vme = 0x00; break;
+ case NVKM_ENGINE_VP :
+ case NVKM_ENGINE_MSPDEC: vme = 0x01; break;
+ case NVKM_SUBDEV_BAR : vme = 0x06; break;
+ case NVKM_ENGINE_MSPPP :
+ case NVKM_ENGINE_MPEG : vme = 0x08; break;
+ case NVKM_ENGINE_BSP :
+ case NVKM_ENGINE_MSVLD : vme = 0x09; break;
+ case NVKM_ENGINE_CIPHER:
+ case NVKM_ENGINE_SEC : vme = 0x0a; break;
+ case NVKM_ENGINE_CE0 : vme = 0x0d; break;
default:
continue;
}
projects / GitHub / exynos8895 / android_kernel_samsung_universal8895.git / commitdiff