clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor

The DDR1 PLL on the A33 is an oddball amongst the A33 CCU clocks.
It is a clock multiplier, with the effective multiplier in the
range of 12 ~ 255 and no offset between the multiplier value and
the value programmed into the register.

Implement the zero offset and minimum value of 12 for this clock.

Fixes: d05c748bd730 ("clk: sunxi-ng: Add A33 CCU support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index a7b3c08ed0e232c0cf41ae419f4980bf1614590e..56370c2c7f98ca2af2d428058ed92fe28cded700 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -159,13 +159,17 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
                                        BIT(28),        /* lock */
                                        CLK_SET_RATE_UNGATE);
 
-/* TODO: Fix N */
-static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
-                                 "osc24M", 0x04c,
-                                 8, 6,                 /* N */
-                                 BIT(31),              /* gate */
-                                 BIT(28),              /* lock */
-                                 CLK_SET_RATE_UNGATE);
+static struct ccu_mult pll_ddr1_clk = {
+       .enable = BIT(31),
+       .lock   = BIT(28),
+       .mult   = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 6, 0, 12, 0),
+       .common = {
+               .reg            = 0x04c,
+               .hw.init        = CLK_HW_INIT("pll-ddr1", "osc24M",
+                                             &ccu_mult_ops,
+                                             CLK_SET_RATE_UNGATE),
+       },
+};
 
 static const char * const cpux_parents[] = { "osc32k", "osc24M",
                                             "pll-cpux" , "pll-cpux" };