perf/amd/uncore: Clean up per-family setup

Fam16h is the same as the default one, remove it. Turn the switch-case
into a simple if-else.

No functionality change.

Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/20170410122047.3026-3-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index abd4b9064fba02dfd9e93c5bc9b279d86e7244d4..975f24f6e238e701be9d7858a71669de69b59dee 100644 (file)
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -514,45 +514,28 @@ static int __init amd_uncore_init(void)
        if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
                return -ENODEV;
 
-       switch(boot_cpu_data.x86) {
-               case 23:
-                       /* Family 17h: */
-                       num_counters_nb = NUM_COUNTERS_NB;
-                       num_counters_llc = NUM_COUNTERS_L3;
-                       /*
-                        * For Family17h, the NorthBridge counters are
-                        * re-purposed as Data Fabric counters. Also, support is
-                        * added for L3 counters. The pmus are exported based on
-                        * family as either L2 or L3 and NB or DF.
-                        */
-                       amd_nb_pmu.name = "amd_df";
-                       amd_llc_pmu.name = "amd_l3";
-                       format_attr_event_df.show = &event_show_df;
-                       format_attr_event_l3.show = &event_show_l3;
-                       break;
-               case 22:
-                       /* Family 16h - may change: */
-                       num_counters_nb = NUM_COUNTERS_NB;
-                       num_counters_llc = NUM_COUNTERS_L2;
-                       amd_nb_pmu.name = "amd_nb";
-                       amd_llc_pmu.name = "amd_l2";
-                       format_attr_event_df = format_attr_event;
-                       format_attr_event_l3 = format_attr_event;
-                       break;
-               default:
-                       /*
-                        * All prior families have the same number of
-                        * NorthBridge and Last Level Cache counters
-                        */
-                       num_counters_nb = NUM_COUNTERS_NB;
-                       num_counters_llc = NUM_COUNTERS_L2;
-                       amd_nb_pmu.name = "amd_nb";
-                       amd_llc_pmu.name = "amd_l2";
-                       format_attr_event_df = format_attr_event;
-                       format_attr_event_l3 = format_attr_event;
-                       break;
+       if (boot_cpu_data.x86 == 0x17) {
+               /*
+                * For F17h, the Northbridge counters are repurposed as Data
+                * Fabric counters. Also, L3 counters are supported too. The PMUs
+                * are exported based on  family as either L2 or L3 and NB or DF.
+                */
+               num_counters_nb           = NUM_COUNTERS_NB;
+               num_counters_llc          = NUM_COUNTERS_L3;
+               amd_nb_pmu.name           = "amd_df";
+               amd_llc_pmu.name          = "amd_l3";
+               format_attr_event_df.show = &event_show_df;
+               format_attr_event_l3.show = &event_show_l3;
+       } else {
+               num_counters_nb           = NUM_COUNTERS_NB;
+               num_counters_llc          = NUM_COUNTERS_L2;
+               amd_nb_pmu.name           = "amd_nb";
+               amd_llc_pmu.name          = "amd_l2";
+               format_attr_event_df      = format_attr_event;
+               format_attr_event_l3      = format_attr_event;
        }
-       amd_nb_pmu.attr_groups = amd_uncore_attr_groups_df;
+
+       amd_nb_pmu.attr_groups  = amd_uncore_attr_groups_df;
        amd_llc_pmu.attr_groups = amd_uncore_attr_groups_l3;
 
        if (boot_cpu_has(X86_FEATURE_PERFCTR_NB)) {